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In this work, we have investigated numerical techniques to determine the breakdown behavior of complex semiconductor devices using two-dimensional simulation. In particular, we have augmented the device simulator SEPSIP with a capability for handling single and multiple floating field rings, and for handling devices with slanted edges. We have furthermore improved the grid width selection algorithm in SEPSIP. A capability for plotting equi-field contours was added to the code. Finally, all system dependencies were removed from the SEPSIP code, and a new version of SEPSIP (Version 2.0) was generated which can be executed on any PC/XT, PC/AT, or PC/386 compatible computer. This eliminates the need for transfering files back and forth between the PC, which had formerly been used as an I/O processor, and the VAX, which was used for numerically intensive computations. It also makes the code more accessible to scientists and engineers who are working in this important research area.

by Pun Kong-Pang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 94-[96]). / Acknowledgement --- p.i / Abstract --- p.iii / List of Tables --- p.vii / List of Figures --- p.viii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Role of Device Simulation --- p.2 / Chapter 1.2 --- Classification of Device Models --- p.3 / Chapter 1.3 --- Sections of a Typical Simulator --- p.6 / Chapter 1.4 --- Arrangement of This Thesis --- p.7 / Chapter 2 --- Classical Physical Model --- p.9 / Chapter 2.1 --- Carrier Densities --- p.12 / Chapter 2.2 --- Space Charge --- p.14 / Chapter 2.3 --- Carrier Mobilities --- p.15 / Chapter 2.4 --- Generation and Recombination --- p.17 / Chapter 2.5 --- Modeling of Device Boundaries --- p.20 / Chapter 2.6 --- Limits of Classical Device Modeling --- p.22 / Chapter 3 --- Computational Aspects --- p.23 / Chapter 3.1 --- Normalization --- p.24 / Chapter 3.2 --- Discretization --- p.26 / Chapter 3.2.1 --- Finite Difference Method --- p.26 / Chapter 3.2.2 --- Finite Element Method --- p.27 / Chapter 3.3 --- Nonlinear Systems --- p.28 / Chapter 3.3.1 --- Newton's Method --- p.28 / Chapter 3.3.2 --- Gummel's Method and its modification --- p.29 / Chapter 3.3.3 --- Comparison and discussion --- p.30 / Chapter 3.4 --- Linear System and Sparse Matrix --- p.32 / Chapter 4 --- Cubic Spline Wavelet Collocation Method for PDEs --- p.34 / Chapter 4.1 --- Cubic spline scaling functions and wavelets --- p.35 / Chapter 4.1.1 --- Approximation for a function in H2(I) --- p.43 / Chapter 4.2 --- Wavelet interpolation --- p.45 / Chapter 4.2.1 --- Interpolant operator Ivo in Vo --- p.45 / Chapter 4.2.2 --- Interpolation operator IWjf in Wj --- p.47 / Chapter 4.3 --- Derivative Matrices --- p.51 / Chapter 4.3.1 --- First derivative matrix --- p.51 / Chapter 4.3.2 --- Second derivative matrix --- p.53 / Chapter 4.4 --- Wavelet Collocation Method for Solving Device Equations --- p.55 / Chapter 4.4.1 --- Steady state solution --- p.57 / Chapter 4.4.2 --- Transient solution --- p.58 / Chapter 4.5 --- Reducing Collocation Points --- p.59 / Chapter 4.5.1 --- Error evaluation --- p.59 / Chapter 4.5.2 --- Deleting collocation points --- p.61 / Chapter 5 --- Numerical Results --- p.64 / Chapter 5.1 --- P-N Junction Diode --- p.64 / Chapter 5.1.1 --- Steady state solution --- p.69 / Chapter 5.1.2 --- Transient solution --- p.76 / Chapter 5.1.3 --- Convergence --- p.79 / Chapter 5.2 --- Bipolar Transistor --- p.81 / Chapter 5.2.1 --- Boundary Model --- p.82 / Chapter 5.2.2 --- DC Solution --- p.83 / Chapter 5.2.3 --- Transient Solution --- p.89 / Chapter 6 --- Conclusions --- p.92 / Bibliography --- p.94

by Chan Chung-Kei, Thomas. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 125-[129]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Semiconductor Device Physics --- p.5 / Chapter 2.1 --- IC Design Methodology --- p.6 / Chapter 2.1.1 --- System Level --- p.7 / Chapter 2.1.2 --- Circuit Level --- p.7 / Chapter 2.1.3 --- Device Level --- p.8 / Chapter 2.1.4 --- Process Level --- p.8 / Chapter 2.2 --- Classification of Device Models --- p.8 / Chapter 2.2.1 --- Circuit Models --- p.9 / Chapter 2.2.2 --- Physical Models --- p.10 / Chapter 2.3 --- Classical Drift-Diffusion model --- p.13 / Chapter 2.3.1 --- Basic Governing Equations in Semiconductors --- p.13 / Chapter 2.3.2 --- Shockley-Read-Hall Recombination Statics --- p.15 / Chapter 2.3.3 --- Boundary Conditions --- p.18 / Chapter 2.4 --- pn Junction at equilibrium --- p.20 / Chapter 2.4.1 --- The depletion approximation --- p.23 / Chapter 2.4.2 --- Current-voltage Characteristics --- p.26 / Chapter 3 --- Iteration Scheme --- p.30 / Chapter 3.1 --- Gummel's iteration scheme --- p.31 / Chapter 3.2 --- Modified Gummel's iteration scheme --- p.35 / Chapter 3.3 --- Solution of Differential Equation --- p.38 / Chapter 3.3.1 --- Finite Difference Method --- p.38 / Chapter 3.3.2 --- Moment Method --- p.39 / Chapter 4 --- Theory of Wavelets --- p.43 / Chapter 4.1 --- Multi-resolution Analysis --- p.43 / Chapter 4.1.1 --- Example of MRA with Haar Wavelet --- p.46 / Chapter 4.2 --- Orthonormal basis of Wavelets --- p.52 / Chapter 4.3 --- Fast Wavelet Transform --- p.56 / Chapter 4.4 --- Wavelets on the interval --- p.62 / Chapter 5 --- Galerkin-Wavelet Method --- p.66 / Chapter 5.1 --- Wavelet-based Moment Methods --- p.67 / Chapter 5.1.1 --- Wavelet transform on the stiffness matrix --- p.67 / Chapter 5.1.2 --- Wavelets as basis functions --- p.68 / Chapter 5.2 --- Galerkin-Wavelet method --- p.69 / Chapter 5.2.1 --- Boundary Conditions --- p.73 / Chapter 5.2.2 --- Adaptive Scheme --- p.74 / Chapter 5.2.3 --- The Choice of Classes of Wavelet Bases --- p.76 / Chapter 6 --- Numerical Results --- p.80 / Chapter 6.1 --- Steady State Solution --- p.81 / Chapter 6.1.1 --- Daubechies Wavelet N = 2 --- p.82 / Chapter 6.1.2 --- Daubechies Wavelet N=5 --- p.84 / Chapter 6.1.3 --- Discussion on Daubechies wavelets N = 2 and N=5 --- p.86 / Chapter 6.2 --- Transient Solution --- p.91 / Chapter 6.3 --- Convergence --- p.99 / Chapter 7 --- Conclusion --- p.103 / Chapter A --- Derivation for steady state --- p.107 / Chapter A.1 --- Generalized Moll-Ross Relation --- p.107 / Chapter A.2 --- Linearization of PDEs --- p.110 / Chapter B --- Derivation for transient state --- p.113 / Chapter C --- Notation --- p.119 / Chapter D --- Elements in the Stiffness Matrix --- p.122 / Bibliography --- p.125

A new method for transient simulation of integrated circuits has been developed and investigated. The method utilizes expansion of circuit variables into Chebyshev series. A prototype computer simulation program based on this technique has been implemented and applied in the transient simulation of several MOS circuits. The results have been compared with those generated by SPICE. The method has been also combined with the waveform relaxation technique. Several algorithms were developed using the Gauss-Seidel and Gauss-Jacobi iterative procedures. The algorithms based on the Gauss-Seidel iterative procedure were implemented in the prototype software. They offer substantial CPU time savings in comparison with SPICE without compromising the accuracy of solutions. A description of the prototype computer simulation program and a summary of the results of simulation experiments are included.

A simulation program has been developed to facilitate the investigation and analysis of power semiconductor devices under the reverse-bias condition. The electrostatic potential distribution is solved by using Poisson's equation alone, with particular attention to the neighborhood of avalanche breakdown. Because of its generality and efficiency, the program emerges as a powerful engineering tool for the design of power devices incorporating special junction termination techniques. Results are presented for a DMOS structure to illustrate the improvement in breakdown voltage when a field plate is applied. Numerical solution techniques for solving elliptic partial differential equations in a multi-material domain are discussed. The discretization of this domain is nonuniform in general due to its highly nonuniform physical parameters. By careful selection of grid lines near interfaces, the difference equation coefficients are considerably simplified. The resultant matrix of coefficients is symmetric even though Neumann boundary conditions are specified.

Two-dimensional numerical simulation was used to study the scaling properties of SOI p-MOSFETs. Based on the design criteria for the threshold voltage and DIBL, a set of design curves for different designs was developed. Data for subthreshold slope, SCE and threshold voltage sensitivity to silicon film thickness are also given. Results show that short-channel effects can be controlled by increasing the doping level or by thinning the silicon film thickness. The first approach is more effective for p+ gate design with high body doping, while the second approach is much more effective for n+ gate design with low body doping. Then+ gate design is more suited for the design of fully depleted (FD) devices since we need to keep the doping low to minimize the threshold adjustment implant dose and to use thin silicon films to control the SCE. The design of both p-MOSFET and Si 1-xGex p-MOSFET requires the implantation for the threshold voltage adjustment. The p+ gate design is more suited for the partially depleted (PD) or near-fully depleted device design since we need to use high doping for the threshold voltage adjustment and this results in large threshold voltage sensitivity to silicon film thickness for FD devices. The design of Si SOI p-MOSFET is done by properly adjusting the body doping. For the Si1-xGex SOI p-MOSFET large reduction in VTH requires large body doping. This increases the parasitic capacitances and slows down the device.

With increasing demand for complex and faster circuits, CMOS technologies are progressing towards the deep-submicron level. Process complexity increases dramatically, and costly techniques are to be developed to create dense field isolation and shallow junctions. Silicon-On-Insulator (SOI) may solve some of these problems. On the other hand, strained Si 1_xGex layers have been successfully grown on Si substrates and demonstrated much higher hole mobility than bulk Si. This can be used to build high-mobility p-MOSFET with a buried Si 1_xGex channel. A high mobility p-MOSFET would improve both the circuit speed and the level of integration. The purpose of the present study was to model and simulate the effective mobility (μeff) of SOI Si 1-xGex p-MOSFET, and to investigate the suitability of local mobility models provided by simulator MEDICI for studying SOI Si 1_xGex p-MOSFET. The simulation is performed by using the two-dimensional device simulation program (MEDICI). The design parameters, such as Si-cap thickness, Ge profile and back-gate bias, were also investigated. A long channel (6μ) and a short channel (0.25μ) SOI and bulk Si 1_xGex p MOSFET were used for the study. Simulation reveals good effective mobility μeff match with experimental results if Si Ge channel of p-MOSFET can simply be treated like a bulk silicon with mobility 250cm2 /Vs. Mobility models provided by MEDICI are two types: a) mobility model (SRFMOB2) that is dependent on transverse electric field only at Si/ Si02 interface, which means that the effective mobility is a function of grid spacing at Si/ Si02 interface, and b) mobility models (PRPMOB, LSMMOB and HPMOB) that are dependent on transverse electric field anywhere in the device. PRPMOB and LSMMOB produce very good μef f and are insensitive to the grid spacing. HP MOB gives slight over estimation of effective mobility μef f. Silicon cap thickness can significantly influence the effective mobility μef f. In general, the thin silicon cap have better effective mobility μef f, but it is limited by manufacturing process. Graded Si 1_:z:Ge:z: channel presents nearly 100% improvement of effective mobility μeff for p-MOSFET over its bulk counterpart. This improvement is sustained up to gate voltage of 2.5 V. Simulation also indicates that large improvement of effective mobility μef f requires higher Ge concentration at the top of SiGe channel with steep grading. The influence of back-gate bias on μeff is small, hence, SOI SiGe MOSFET is well suited to building CMOS circuits.