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Design and implementation of multi-GHz energy-efficient asynchronous pipelined circuits in MOS current-mode logic /Kwan, Tin Wai, January 1900 (has links)
Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 97-99). Also available in electronic format on the Internet.
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Limitations and opportunities for wire length prediction in gigascale integrationAnbalagan, Pranav. January 2007 (has links)
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007. / Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.
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Design and optimization of MOS current-mode logic circuits using mathematical programming /Khabiri, Shahnam, January 1900 (has links)
Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 77-78). Also available in electronic format on the Internet.
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Delay Test Scan Flip-Flop c(DTSFF) design and its applications for scan based delay testingXu, Gefu, Singh, Adit D. January 2007 (has links) (PDF)
Dissertation (Ph.D.)--Auburn University, 2007. / Abstract. Vita. Includes bibliographic references (p.107-111).
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