Continuous-time (CT) data conversion and continuous-time digital signal processing (DSP) are an interesting alternative to conventional methods of signal conversion and processing. This alternative proposes time-based encoding that may not suffer from aliasing; shows superior spectral properties (e.g. no quantization noise floor); and enables time-based, event-driven, flexible signal processing using digital circuits, thus scaling well with technology. Despite these interesting features, this approach has so far been limited by the CT encoder, due to both its relatively poor energy efficiency and the constraints it imposes on the subsequent CT DSP. In this thesis, we present three principles that address these limitations and help improve the CT ADC/DSP system. First, an adaptive-resolution encoding scheme that achieves first-order reconstruction with simple circuitry is proposed. It is shown that for certain signals, the scheme can significantly reduce the number of samples generated per unit of time for a given accuracy compared to schemes based on zero-order-hold reconstruction, thus promising to lead to low dynamic power dissipation at the system level. Presented next is a novel time-based CT ADC architecture, and associated encoding scheme, that allows a compact, energy-efficient circuit implementation, and achieves first-order quantization error spectral shaping. The design of a test chip, implemented in a 0.65-V 28-nm FDSOI process, that includes this CT ADC and a 10-tap programmable FIR CT DSP to process its output is described. The system achieves 32 dB – 42 dB SNDR over a 10 MHz – 50 MHz bandwidth, occupies 0.093 mm2, and dissipates 15 µW–163 µW as the input amplitude goes from zero to full scale. Finally, an investigation into the possibility of CT encoding using voltage-controlled oscillators is undertaken, and it leads to a CT ADC/DSP system architecture composed primarily of asynchronous digital delays. The latter makes the system highly digital and technology-scaling-friendly and, hence, is particularly attractive from the point of view of technology migration. The design of a test chip, where this delay-based CT ADC/DSP system architecture is used to implement a 16-tap programmable FIR filter, in a 1.2-V 28-nm FDSOI process, is described. Simulations show that the system will achieve a 33 dB – 40 dB SNDR over a 600 MHz bandwidth, while dissipating 4 mW.

Thesis. 1978. M.S.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaves 185-191. / M.S.

Le, Jilin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (p. 57-59). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- How Many Packets Can We Encode? --- p.2 / Chapter 1.2 --- Coding-Aware Routing --- p.3 / Chapter 2 --- Related Work --- p.6 / Chapter 3 --- Performance Analysis of COPE --- p.8 / Chapter 3.1 --- Introduction --- p.8 / Chapter 3.2 --- Coding Structure: Characterization and Properties --- p.9 / Chapter 3.2.1 --- Assumptions and notations --- p.9 / Chapter 3.2.2 --- Optimum Throughput in a Coding Structure --- p.10 / Chapter 3.2.3 --- The Upper Bound of Maximum Encoding Number --- p.11 / Chapter 3.3 --- Coding Performance under Random Access Link-Scheduling --- p.14 / Chapter 3.3.1 --- Key Intuition --- p.14 / Chapter 3.3.2 --- Calculating the Average Encoding Number --- p.15 / Chapter 3.3.3 --- Case Studies --- p.18 / Chapter 3.3.4 --- Will Delaying Strategy at the Coding Node Help? --- p.21 / Chapter 3.4 --- Fundamental Limits of the Coding Scheme --- p.22 / Chapter 3.5 --- Verification of the Analysis --- p.27 / Chapter 3.5.1 --- Simulation Results in a Single Coding Structure --- p.27 / Chapter 3.5.2 --- Simulation Results under 802.11 and General Networks --- p.29 / Chapter 3.6 --- Potential Applications --- p.31 / Chapter 3.7 --- Conclusion --- p.31 / Chapter 4 --- Distributed Coding-Aware Routing --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- "The ""CodingH+Routing"" Discovery" --- p.34 / Chapter 4.2.1 --- Assumptions --- p.34 / Chapter 4.2.2 --- General Coding Conditions --- p.35 / Chapter 4.2.3 --- "Distributed ""Coding+Routing"" Discovery" --- p.36 / Chapter 4.2.4 --- An Illustrative Example --- p.38 / Chapter 4.2.5 --- Overheads of Coding+Routing Discovery --- p.39 / Chapter 4.3 --- Defining Coding-Aware Routing Metric --- p.40 / Chapter 4.3.1 --- Review of Current Routing Metrics --- p.40 / Chapter 4.3.2 --- Desirable Properties of Coding-aware Routing Metric --- p.42 / Chapter 4.3.3 --- Assumptions on Encoded Transmission --- p.42 / Chapter 4.3.4 --- "Interpreting the ""Free-Ride"" Benefit" --- p.43 / Chapter 4.3.5 --- Modified Queue Length --- p.44 / Chapter 4.3.6 --- MIQ: Modified Interference Queue Length --- p.46 / Chapter 4.3.7 --- CRM: Coding-aware Routing Metric --- p.47 / Chapter 4.4 --- Implementation Details --- p.48 / Chapter 4.5 --- Simulation Results --- p.49 / Chapter 4.5.1 --- Results from Illustrative Scenarios --- p.50 / Chapter 4.5.2 --- Results from Mesh Networks --- p.52 / Chapter 4.6 --- Conclusion --- p.55 / Chapter 5 --- Conclusion --- p.56 / Bibliography --- p.57

The analog to digital converter (ADC) samples a continuous analog signal and produces a stream of digital words which approximate the analog signal. The conversion process introduces noise into the digital signal. In the case of an ideal ADC, where all noise sources are ignored, the noise due to the quantization process remains. The resolution of the ADC is defined by how many bits are in the digital output word. The amount of quantization noise is clearly related to the resolution of the ADC. Reducing the quantization noise results in higher effective resolution.

Multi-level decision feedback equalization (MDFE) is a sampled signal processing technique for data recovery from magnetic recording channels which use the 2/3(1,7) run length limited code. The key adaptive feedback loops in MDFE are those which perform the timing recovery, gain recovery, dc offset detection, and adaptive equalization of the feedback equalizer. The algorithms used by these adaptive loops are derived from the channel error which is the deviation of the equalized signal from its ideal value. It is advantageous to convert this error signal to a digital value using a flash analog-to-digital converter (flash ADC) to simplify the implementation of the adaptive loops. In this thesis, a scheme to place the thresholds of the flash ADC is presented. The threshold placement has been optimized based on the steady-state probability density function (pdf) of the signal to be quantized. The resolution constraints imposed by this quantization scheme on the adaptive loops has been characterized. As the steady-state assumption for the signal to be quantized is not valid during the transient state of the adaptive loops, the loop transients with this quantization scheme have been analyzed through simulations. The conditions under which the channel can recover from a set of start-up errors and converge successfully into steady-state have been specified. The steady-state channel performance with the noise introduced by the iterative nature of the adaptive loops along with this quantization scheme has also been verified. / Graduation date: 1997

Paul Moroney, Alan S. Willsky, Paul K. Houpt. / Bibliography: p. 52-54. / "August, 1981" / "NASA Ames ... Grant NGL-22-009-124"

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Floating-point arithmetic is attractive for the implementation for a variety of Digital Signal Processing (DSP) applications because it allows the designer and user to concentrate on the algorithms and architecture without worrying about numerical issues. In the past, many DSP applications used fixed point arithmetic due to the high cost (in delay, silicon area, and power consumption) of floating-point arithmetic units. In the realization of modern general purpose processors, fused floating-point multiply add units have become attractive since their delay and silicon area is often less than that of a discrete floating-point multiplier followed by a floating point adder. Further the accuracy is improved by the fused implementation since rounding is performed only once (after the multiplication and addition). This work extends the consideration of fused floating-point arithmetic to operations that are frequently encountered in DSP. The Fast Fourier Transform is a case in point since it uses a complex butterfly operation. For a radix-2 implementation, the butterfly consists of a complex multiply and the complex addition and subtraction of the same pair of data. For a radix-4 implementation, the butterfly consists of three complex multiplications and eight complex additions and subtractions. Both of these butterfly operations can be implemented with two fused primitives, a fused two-term dot-product unit and a fused add-subtract unit. The fused two-term dot-product multiplies two sets of operands and adds the products as a single operation. The two products do not need to be rounded (only the sum is normalized and rounded) which reduces the delay by about 15% while reducing the silicon area by about 33%. For the add-subtract unit, much of the complexity of a discrete implementation comes from the need to compare the operand exponents and align the significands prior to the add and the subtract operations. For the fused implementation, sharing the comparison and alignment greatly reduces the complexity. The delay and the arithmetic results are the same as if the operations are performed in the conventional manner with a floating-point adder and a separate floating-point subtracter. In this case, the fused implementation is about 20% smaller than the discrete equivalent. / text

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