Implementing Shamir's secret sharing scheme using floating point arithmetic would provide a faster and more efficient secret sharing scheme due to the speed in which GPUs perform floating point arithmetic. However, with the loss of a finite field, properties of a perfect secret sharing scheme are not immediately attainable. The goal is to analyze the plausibility of Shamir's secret sharing scheme using floating point arithmetic achieving the properties of a perfect secret sharing scheme and propose improvements to attain these properties. Experiments indicate that property 2 of a perfect secret sharing scheme, "Any k-1 or fewer participants obtain no information regarding the shared secret", is compromised when Shamir's secret sharing scheme is implemented with floating point arithmetic. These experimental results also provide information regarding possible solutions and adjustments. One of which being, selecting randomly generated points from a smaller interval in one of the proposed schemes of this thesis. Further experimental results indicate improvement using the scheme outlined. Possible attacks are run to test the desirable properties of the different schemes and reinforce the improvements observed in prior experiments. / by Timothy Finemore. / Thesis (M.S.)--Florida Atlantic University, 2012. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2012. Mode of access: World Wide Web.

The goal of a speech enhancement algorithm is to remove noise and recover the original signal with as little distortion and residual noise as possible. Most successful real-time algorithms thereof have done in the frequency domain where the frequency amplitude of clean speech is estimated per short-time frame of the noisy signal. The state of-the-art short-time spectral amplitude estimator algorithms estimate the clean spectral amplitude in terms of the power spectral density (PSD) function of the noisy signal. The PSD has to be computed from a large ensemble of signal realizations. However, in practice, it may only be estimated from a finite-length sample of a single realization of the signal. Estimation errors introduced by these limitations deviate the solution from the optimal. Various spectral estimation techniques, many with added spectral smoothing, have been investigated for decades to reduce the estimation errors. These algorithms do not address significantly issue on quality of speech as perceived by a human. This dissertation presents analysis and techniques that offer spectral refinements toward speech enhancement. We present an analytical framework of the effect of spectral estimate variance on the performance of speech enhancement. We use the variance quality factor (VQF) as a quantitative measure of estimated spectra. We show that reducing the spectral estimator VQF reduces significantly the VQF of the enhanced speech. The Autoregressive Multitaper (ARMT) spectral estimate is proposed as a low VQF spectral estimator for use in speech enhancement algorithms. An innovative method of incorporating a speech production model using multiband excitation is also presented as a technique to emphasize the harmonic components of the glottal speech input. / The preconditioning of the noisy estimates by exploiting other avenues of information, such as pitch estimation and the speech production model, effectively increases the localized narrow-band signal-to noise ratio (SNR) of the noisy signal, which is subsequently denoised by the amplitude gain. Combined with voicing structure enhancement, the ARMT spectral estimate delivers enhanced speech with sound clarity desirable to human listeners. The resulting improvements in enhanced speech are observed to be significant with both Objective and Subjective measurement. / by Werayuth Charoenruengkit. / Vita. / Thesis (Ph.D.)--Florida Atlantic University, 2009. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2009. Mode of access: World Wide Web.

by Lee Sui Yip. / Thesis (M.Sc.)--Chinese University of Hong Kong, 1992. / Includes bibliographical references. / Chapter Chapter1 --- Introduction / Chapter 1.1 --- Objectives of Common Channel Signalling --- p.1.1 / Chapter 1.1.1 --- Channel Associated Signalling --- p.1-1 / Chapter 1.1.2 --- Common Channel Signalling --- p.1.2 / Chapter 1.2 --- Functional Description --- p.1.3 / Chapter 1.3 --- Signalling Network Basics --- p.1.5 / Chapter 1.4 --- Network Topology --- p.1.9 / Chapter 1.5 --- Signalling Messages --- p.1.13 / Chapter Chapter2 --- Common Channel Signalling No. 7 Network of Hong Kong Telephone / Chapter 2.1 --- System Performance Criteria --- p.2.1 / Chapter 2.1.1 --- Post Dialing Delay --- p.2.2 / Chapter 2.1.2 --- Availability --- p.2.3 / Chapter 2.1.3 --- Survivabiliy --- p.2.3 / Chapter 2.2 --- Implementation Considerations --- p.2.4 / Chapter 2.2.1 --- System Constraints --- p.2.4 / Chapter 2.2.2 --- Number of Signal Transfer Points --- p.2.5 / Chapter 2.2.3 --- Signalling Modes and Assignments --- p.2.6 / Chapter 2.2.4 --- Signalling Link-sets and Diversity --- p.2.7 / Chapter 2.2.5 --- Post Dialing Delay --- p.2.7 / Chapter 2.3 --- The Common Channel Signalling Network of Hong Kong Telephone --- p.2.7 / Chapter Appendix : --- Queuing Delay Estimation --- p.2.9 / Chapter Chapter3 --- Message Routing Policy / Chapter 3.1 --- Originating Signalling Point --- p.3.2 / Chapter 3.2 --- Selection of Signalling Links --- p.3.3 / Chapter 3.3 --- Signal Transfer Points --- p.3.5 / Chapter 3.3.1 --- Same Cluster --- p.3.6 / Chapter 3.3.2 --- Adjacent Clusters --- p.3.6 / Chapter 3.3.3 --- Distant Clusters --- p.3.7 / Chapter 3.4 --- Destination Signalling Point --- p.3.8 / Chapter Appendix : --- STP Stages Estimation --- p.3.9 / Chapter Chapter4 --- Building the Simulation Model / Chapter 4.1 --- Modelling Objective --- p.4.1 / Chapter 4.2 --- The Cluster Level Model --- p.4.2 / Chapter 4.2.1 --- Message Generation --- p.4.2 / Chapter 4.2.2 --- Modelling Message Routing --- p.4.3 / Chapter 4.2.3 --- Modelling Failures --- p.4.5 / Chapter 4.2.4 --- The Simulation Procedures --- p.4.6 / Chapter 4.2.4.1 --- Processes --- p.4.6 / Chapter 4.2.4.2 --- Permanent Entities --- p.4.8 / Chapter 4.2.4.3 --- Initialization Routines --- p.4.9 / Chapter 4.3 --- The Signalling Point Level Model --- p.4.11 / Chapter 4.3.1 --- Message Generation and Routing --- p.4.13 / Chapter 4.3.2 --- Simulation Procedures --- p.4.13 / Chapter Chapter5 --- Network Planning and Evaluation with the Simulation Model / Chapter 5.1 --- Model Testing --- p.5.1 / Chapter 5.2 --- Comparison with Analytical Results --- p.5.2 / Chapter 5.3 --- Modelling with 1 STP Failure --- p.5.5 / Chapter 5.4 --- Simulation with Measured Data --- p.5.8 / Chapter 5.5 --- Network Performance Evaluation --- p.5.15 / Chapter 5.5.1 --- Normal Conditions --- p.5.15 / Chapter 5.5.2 --- STP Failures --- p.5.16 / Chapter 5.5.3 --- Signalling Link-set Failures --- p.5.17 / Chapter 5.6 --- Network Planning --- p.5.19 / Chapter 5.6.1 --- Re-allocation of Signalling Points --- p.5.21 / Chapter 5.6.2 --- Re-configuration of Signalling Network --- p.5.21 / Chapter 5.6.3 --- Associated Link Provision Policy --- p.5.22 / Chapter 5.6.4 --- New Message Routing Policy --- p.5.22 / Discussion and Conclusion / References

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Includes bibliographical references. / by Bruce R. Musicus. / Ph.D.

Includes bibliographical references (leaves 277-284) Presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology.

The objective of the thesis is concerned on the problem of detecting superpositional signals in a wireless channel. In many wireless systems, an observed signal is commonly represented as a linear combination of the transmitted signal with the interfering signals dispersed in space and time. These systems are generally known as the interference-limited systems. The mathematical model of these systems is generally referred as a superpositional model. A distinguished characteristic of signal transmission in a time-varying wireless channel is that the channel process is not known a priori. Reliable signal reception inherently requires exploiting the structure of the interfering signals under channel uncertainty. Our goal is to design computational efficient receivers for various interference-limited systems by using advanced statistical signal processing techniques. The thesis consists of four main parts. Firstly, we have proposed a novel Multi-Input Multi-Output (MIMO) signal detector, known as the neighbourhood exploring detector (NED). According to the maximum likelihood principle, the space time MIMO detection problem is equivalent to a NP-hard combinatorial optimization problem. The proposed detector is a sub-optimal maximum likelihood detector which eliminates exhaustive multidimensional searches. Secondly, we address the problem of signal synchronization for Global Positioning System (GPS) in a multipath environment. The problem of multipath mitigation constitutes a joint estimation of the unknown amplitudes, phases and time delays of the linearly combined signals. The complexity of the nonlinear joint estimation problem increases exponentially with the number of signals. We have proposed two robust GPS code acquisition systems with low complexities. Thirdly, we deal with the problem of multipath mitigation in the spatial domain. A GPS receiver integrated with the Inertial Navigation System (INS) and a multiple antenna array is considered. We have designed a software based GPS receiver which effectively estimates the directions of arrival and the time of arrival of the linearly combined signals. Finally, the problem of communications with unknown channel state information is investigated. Conventionally, the information theoretical communication problem and the channel estimation problem are decoupled. However the training sequence, which facilitates the estimation of the channel, reduces the throughput of the channel. We have analytically derived the optimal length of the training sequence which maximizes the mutual information in a block fading channel.

The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

Several papers propose the use of on-line arithmetic for signal processing applications implemented on FPGAs. Although those papers provide reasonable arguments for the use of on-line arithmetic, they give only inadequate or incomplete comparisons of the proposed on-line designs to other state of the art solutions on FPGAs. In this thesis, the design, implementation and evaluation of on-line modules and networks for DSP applications, using FPGAS as the target technology, are shown. The presented designs of the modules are highly optimized for the target hardware, which allows a significant increase in efficiency compared to standard on-line designs. The design process for the networks of on-line modules is described in detail, and a methodology to analyze the dataflow and timing is presented. A comparison of on-line signal processing solutions with other approaches. that are available as IP building blocks or components, is given. It is shown that on-line designs are better in terms of latency but that they can not compete in terms of throughput and area for basic applications like FIR filters. However, it is also shown that on-line designs are able to overtake other approaches as the applications become more sophisticated. e.g. when data dependencies exist, or when non constant multiplicands restrict the use of other approaches, such as serial distributed arithmetic. For these applications, online arithmetic shows, compared to other designs, a lower latency and a significant area reduction, while maintaining a high throughput. Several properties of algorithms for which on-line arithmetic is advantageous are identified in this thesis. With this information, it is possible to determine if an on-line solution for an application should be considered. The conclusions are based on experimental data collected using CAD tools for the Xilinx XC4000 family of chips. All the designs are synthesized for the same type of devices for comparison, avoiding rough estimates of the system performance. This generates a more reliable comparison allowing designers to decide between on-line or conventional approaches for their DSP designs. / Graduation date: 2002

Bruce Ronald Musicus. / Originally published as thesis (Dept. of Electrical Engineering and Computer Science, Ph.D., 1982). / Includes bibliographies. / Supported in part by the Advanced Research Projects Agency monitored by ONR under Contract N00014-81-K-0742 NR-049-506 Supported in part by the National Science Foundation under Grant ECS80-07102

Modern signal processing applications emerging in telecommunication and instrumentation industries have placed an increasing demand for ADCs with higher speed and resolution. The most fundamental challenge in such a progress lies at the heart of the classic signal processing: the Shannon-Nyquist sampling theorem which stated that when sampled uniformly, there is no way to increase the upper frequency in the signal spectrum and still unambiguously represent the signal except by raising the sampling rate. This thesis is dedicated to the exploration of the ways to break through the Shannon-Nyquist sampling rate by applying non-uniform sampling techniques. Time interleaving is probably the most intuitive way to parallel the uniform sampling process in order to achieve a higher sampling rate. Unfortunately, the channel mismatches in the TIADC system make the system an instance of a recurrent non-uniform sampling system whose non-uniformities are detrimental to the performance of the system and need to be calibrated. Accordingly, this thesis proposed a flexible and efficient architecture to compensate for the channel mismatches in the TIADC system. As a key building block in the calibration architecture, the design of the Farrow structured adjustable fractional delay filter has been investigated in detail. A new modified Farrow structure is proposed to design the adjustable FD filters that are optimized for a given range of bandwidth and fractional delays. The application of the Farrow structure is not limited to the design of adjustable fractional delay filters. It can also be used to implement adjustable lowpass, highpass and bandpass filters as well as adjustable multirate filters. This thesis further extends the Farrow structure to the design of filters with adjustable polynomial phase responses. Inspired by the theory of compressive sensing, another contribution of this thesis is to use randomization as a means to overcome the limit of the Nyquist rate. This thesis investigates the impact of random sampling intervals or jitters on the power spectrum of the sampled signal. It shows that the aliases of the original signal can be well shaped by choosing an appropriate probability distribution of the sampling intervals or jitters such that aliases can be viewed as a source of noise in the signal power spectrum. A new theoretical framework has been established to associate the probability mass function of the random sampling intervals or jitters with the aliasing shaping effect. Based on the theoretical framework, this thesis proposes three random sampling architectures, i.e., SAR ADC, ramp ADC and level crossing ADC, that can be easily implemented based on the corresponding standard ADC architectures. Detailed models and simulations are established to verify the effectiveness of the proposed architectures. A new reconstruction algorithm called the successive sine matching pursuit has also been proposed to recover a class of spectrally sparse signals from a sparse set of non-uniform samples onto a denser uniform time grid so that classic signal processing techniques can be applied afterwards.