Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2016-08-09T22:51:25Z No. of bitstreams: 1 CarlosAlbertoDeAlbuquerqueSilva_TESE.pdf: 4568486 bytes, checksum: 5ddf18d55603ffd49ea2899025e1615f (MD5) / Approved for entry into archive by Arlan Eloi Leite Silva (eloihistoriador@yahoo.com.br) on 2016-08-10T23:15:49Z (GMT) No. of bitstreams: 1 CarlosAlbertoDeAlbuquerqueSilva_TESE.pdf: 4568486 bytes, checksum: 5ddf18d55603ffd49ea2899025e1615f (MD5) / Made available in DSpace on 2016-08-10T23:15:49Z (GMT). No. of bitstreams: 1 CarlosAlbertoDeAlbuquerqueSilva_TESE.pdf: 4568486 bytes, checksum: 5ddf18d55603ffd49ea2899025e1615f (MD5) Previous issue date: 2015-09-04 / Ag?ncia Nacional do Petr?leo - ANP / As Redes Neurais Artificiais (RNAs), que constituem uma das ramifica??es da Intelig?ncia Artificial (IA), est?o sendo empregadas como solu??o para v?rios problemas complexos, existentes nas mais diversas ?reas. Para a solu??o destes problemas torna-se indispens?vel que sua implementa??o seja feita em hardware. Em meio as estrat?gias a serem adotadas e satisfeitas durante a fase de projeto e implementa??o das RNAs em hardware, as conex?es entre os neur?nios s?o as que necessitam de maior aten??o. Recentemente, encontram-se RNAs implementadas tanto em circuitos integrados de aplica??o espec?fica (Application Specific Integrated Circuits - ASIC) quanto em circuitos integrados, configurados pelo usu?rio, a exemplo dos Field Programmable Gate Array (FPGAs), que possuem a capacidade de serem reconfigurados parcialmente, em tempo de execu??o, formando, portanto, um Sistema Parcialmente Reconfigur?vel (SPR), cujo emprego proporciona diversas vantagens, tais como: flexibilidade na implementa??o e redu??o de custos. Tem-se observado um aumento considerado no uso destes dispositivos para a implementa??o de RNAs. Diante do exposto, prop?e-se a implementa??o de uma matriz de neur?nios dinamicamente reconfigur?vel no FPGA Virtex 6 da Xilinx, descrita em linguagem de hardware e que possa absorver projetos baseados em plataforma de sistemas embarcados, dedicados ao controle distribu?do de equipamentos normalmente utilizados na ind?stria. Prop?e-se ainda, que a configura??o das topologias das RNAs que possam vir a ser formadas, seja realizada via software. / The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.