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Nesta dissertação estudamos o espectro dinâmico para fluxos 'skew-product' em um fibrado de Banach. Apresentamos uma caracterização para a existência de dicotomia exponencial para tais fluxos e provamos que esta não é destruída sob pequenas perturbações. A dicotomia discreta é uma ferramenta muito útil nesta análise.

This dissertation presents a study of signal deskewing systems in standard CMOS technologies. The objective of this work is to understand the limitations of deskewing systems as they are applied to modern systems and present new architectures to overcome past limitations. Traditional methods for signal deskewing are explored and the general limitations of these methods are identified. Several new architectures are proposed to address the limitations of previous techniques. The systems will be investigated with regard to minimum resolution, programming time, delay, maximum data rate, full scale range, and duty cycle distortion. Several other effects that are critical to the operation of deskewing systems will also be investigated. These effects include overshoot caused by parasitic package inductance, the impact of capacitive terminations, and the effect of mutual inductance between traces. To fulfill the requirements of this study, two deskewing systems are implemented in a 0.25um process. An open-loop system for deskewing wide data busses and a closed-loop system for deskewing a differential pair of lines are both fabricated. Both systems are found to meet the expected performance metrics, providing validation of the proposed techniques. Use of the proposed architectures allows the limitations of previous methods to be overcome. The remaining work is validated through either analytical techniques, simulations, or both where appropriate.

Generalized inverses of matrices are of great importance in the resolution of linear systems and have been extensively studied by many researchers. A collection of some results on generalized inverses of matrices over commutative rings has been provided by K. P. S. Bhaskara Rao (2002). In this thesis, we consider constructing algorithms for finding generalized inverses and generalizing the results collected in Rao's book to the non-commutative case. We first construct an algorithm by using the greatest common divisor to find a generalized inverse of a given matrix over a commutative Euclidean domain. We then build an algorithm for finding a generalized inverse of a matrix over a non-commutative Euclidean domain by using the one-sided greatest common divisor and the least common left multiple. Finally, we explore properties of various generalized inverses including the Moore-Penrose inverse, the group inverse and the Drazin inverse in the non-commutative case.

Nesta dissertação estudamos o espectro dinâmico para fluxos 'skew-product' em um fibrado de Banach. Apresentamos uma caracterização para a existência de dicotomia exponencial para tais fluxos e provamos que esta não é destruída sob pequenas perturbações. A dicotomia discreta é uma ferramenta muito útil nesta análise.

We prove two new results about 0-1-fillings of skew diagrams avoiding long increasing and decreasing chains. In the first half of the thesis, we show that for a large class of skew diagrams, there is a bijection between sparse fillings avoiding an increasing chain of fixed length and sparse fillings avoiding a decreas- ing chain of the same length. In the second half, we extend a known inequality between the number of sparse 0-1-fillings of skew diagrams avoiding an increasing chain of length 2 and a decreasing chain of length 2 to all 0-1-fillings. 1

The applications of generalized inverses of matrices appear in many fields like applied mathematics, statistics and engineering [2]. In this thesis, we discuss generalized inverses of matrices over Ore polynomial rings (also called Ore matrices). We first introduce some necessary and sufficient conditions for the existence of {1}-, {1,2}-, {1,3}-, {1,4}- and MP-inverses of Ore matrices, and give some explicit formulas for these inverses. Using {1}-inverses of Ore matrices, we present the solutions of linear systems over Ore polynomial rings. Next, we extend Roth's Theorem 1 and generalized Roth's Theorem 1 to the Ore matrices case. Furthermore, we consider the extensions of all the involutions ψ on R(x), and construct some necessary and sufficient conditions for ψ to be an involution on R(x)[D;σ,δ]. Finally, we obtain two different explicit formulas for {1,3}- and {1,4}-inverses of Ore matrices. The Maple implementations of our main algorithms are presented in the Appendix. / May 2017

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribed skews with the minimum wire length and acceptable slew rate. Traditional zero-skew clock routing methods are not adequate to address this demand, since they tend to yield excessive wire length for prescribed skew targets. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area, which results in lesser cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper slew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the algorithm can reduce the total wire and buffer capacitance by 60% over an extension of the existing zero-skew routing method.

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis.The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis.The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.