Thèse de doctorat : Sociologie et Anthropologie : Lyon 2 : 2001. / Titre provenant de l'écran-titre. Bibliogr.

No description available.

Thèse (M.A.)--Université de Sherbrooke (Canada), 2007. / Titre de l'écran-titre (visionné le 4 mars 2008). In ProQuest dissertations and theses. Publié aussi en version papier.

Reprend une partie de : Diss. : Fakultät Sozial- und Wirtschaftswissenschaften : Universität Bamberg : 1988. L'autre partie a été publ. à Munich sous le titre "Studien über Gewalt in Familien.

Habilitationsschrift--Berlin--Freie Universität, 1985.

Thèse (D.Ps.)--Université de Sherbrooke (Canada), 2007. / Titre de l'écran-titre (visionné le 24 mars 2009). In ProQuest dissertations and theses. Publié aussi en version papier.

Texte remanié de: Diss.--Münster--Univ., 1993. / Notes bibliogr. Bibliogr. p. 287-296.

Habilitationsschrift--Theologische Fakultät--Zürich, 1994. / Bibliogr. p. 239-241. Index.

abstract: Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250&degC.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235&degC.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage. / Dissertation/Thesis / M.S. Electrical Engineering 2010

The purpose of this project has been twofold: firstly, to develop further FTIR reflectance spectroscopy as a technique for the quantitative characterisation of SOI multilayer structures and secondly, to use it in combination with other techniques, such as RBS/Channelling, XTEM, SIMS, AES and SRP, to investigate the evolution and structure of novel SOI materials. In order to evaluate the FTIR results, many SIMOX samples were fabricated with a wide range of Si and buried SiO2 layer thicknesses with one or two buried oxide layers. The FTIR results are compared to those obtained with the other experimental techniques and with theoretical calculations. We show that, given an "a priori" knowledge of the structure which is used to define the initial structural model, FTIR can be used as a non-destructive, fast, and inexpensive control method for characterising SOI structures. FTIR offers +/-2 nm accuracy in layer thicknesses and +/-5 nm in interfacial region thicknesses, over a wide (0.5 to >10mum) depth range, while for shallower depths an error of 15% on average is likely. FTIR gives Si thickness values which are within 5%, and buried layer or interfacial region thickness values which are within 10% to 20%, from the values obtained by other techniques. The sensitivity to oxygen content variations is down to 5 x 1020 O cm-3 for the top of a Gaussian profile, and 1 X 1022 O cm-3 over a 20 nm thick layer. FTIR gives a value for the retained dose within 5% of the nominal dose for both unannealed and annealed samples. Novel SOI materials, such as deep buried oxide layers and double SIMOX structures were fabricated and characterised, and the processing parameters optimised. We show that, for 2 MeV oxygen implantation into Si at 700°C to a dose of 2 x 1018 O+ cm-2 and after annealing at 1300°C for 6 hours, a buried layer is formed which is continuous but contains Si islands. It is found that by increasing the annealing time to 12 hours, the homogeneity of the buried layer is improved. We propose that an increase of both the oxygen dose and the annealing temperature would result in a higher quality buried oxide layer. The adverse effect of high beam current densities to the sample structure after annealing is demonstrated for the high energy SIMOX samples. We show that double SIMOX structures can be fabricated by a three step process, with one only annealing step at the end. Such structures can be used for Si waveguiding applications and we present preliminary results of waveguiding loss measurements, where a value of 18 dB/cm was obtained.