This paper studies the quality of synthetic speech produced by integrated circuit (IC) hardware using fixed-point arithmetic and Linear Predictive Coding (LPC). A theoretical model explaining the combined effects of finite wordlength and parametric model order is developed. This model is used to predict the results obtained in the experimental phase of this study. In the experimental phase, selected model utterances are synthesized under finite wordlength constraints using LPC parameters. The synthetic speech is evaluated in terms of the log area ratios which define objective speech quality as a parametric distance. A theoretical model is developed to predict the experimental results. Simulations of this model produce data that predict the experimental results. The same information is extracted from the model as that obtained from actually running the fixed-point synthesizer simulator. Since the predictions of the theoretical model agree quite well with the experimental measurements, it is concluded that fixed-point synthesizer performance can be predicted without actually running a complicated and expensive fixed-point synthesizer. Secondly, results obtained from either method clearly indicate that for 15 or 16 bits, ten is the best number of poles to use. Eight useable poles are indicated for 14 bits, while seven are indicated for 13 bits. Based on the results of this study, the use of less than 13 bits for fixed-point calculations is not recommended.