As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work. / text

Not available / text

The ability to remember past experiences enables a system to improve its performance as well as its competence. For example, a system might be able solve problems faster by adapting previous solutions. Additional tasks, such as avoiding unwanted behavior by detecting potential problems, monitoring long-term goals by remembering what subgoals have been achieved, and reflection on past actions, become feasible. As the tasks that an intelligent system accomplishes become more and more complex, so does the experience it acquires in the process. Such experience has a temporal extent and is expressed in terms of concepts and relations with deep semantics associated to them. Memory systems should be able to deal with the temporal aspect of experience, exploit this semantic knowledge for storage and retrieval and do so in a scalable fashion. However, relying just on experience will not achieve a broad coverage, as it needs to be used in conjunction with other reasoning mechanisms. That is why we need the ability to add episodic memory functionality to intelligent systems. Today's knowledge-based systems are complex software applications and the ability to develop them in a modular fashion, using generic, reusable components is essential. We propose to separate the episodic memory from the system that uses it and to build a generic, reusable memory module that can be attached to a variety of applications in order to provide this functionality. Its goal is to provide accurate, scalable, efficient and content-addressable access to prior episodes. Having such a reusable memory module should allow research to focus on the generic aspects of memory representation, organization and retrieval and its interaction with the external application and it should also reduce the complexity of the overall system. In this dissertation we propose a set of general requirements that any memory module should provide regarding memory encoding, storage and retrieval. We present an implementation that satisfies these requirements and evaluate it on three different tasks: plan synthesis, plan recognition and Physics problem solving. The memory module proved easily adaptable to these tasks, providing fast, accurate and scalable retrieval.

Mainstream non-volatile memory technology dominated by the planar Flash transistor with continuous floating-gate has been historically improved in density and performance primarily by means of process scaling, but is currently faced with significant hindrances to its future scaling due to fundamental constraints of electrostatics and reliability. This dissertation is based on exploring two pathways for circumventing scaling limitations of the state-of-the-art Flash memory technology. The first part of the dissertation is based on demonstrating a vertical Flash memory transistor with nanocrystal floating-gate, while the second part is based on developing fundamental understanding of the operation of Phase Change Memory. A vertical Flash transistor can allow the theoretical minimum cell area and a nanocrystal floating-gate on the sidewalls is shown to allow a thinner gate-stack further conducive to scaling while still providing good reliability. Subsequently, the application of a technique of protein-mediated assembly of preformed nanocrystals to the sidewalls of the vertical Flash transistor is also demonstrated and characterized. This technique of ordering pre-formed nanocrystals is beneficial towards achieving reproducible nanocrystal size uniformity and ordering especially in a highly scaled vertical Flash cell, rendering it more amenable to scaling and manufacturability. In both forms, the vertical Flash memory cell is shown to have good electrical characteristics and reliability for the viability of this cell design and implementation. In the remaining part of this dissertation, studies are undertaken towards developing fundamental understanding of the operational characteristics of Phase Change Memory (PCM) technology that is expected to replace floating-gate Flash technology based on its potential for scaling. First, a phenomenon of improving figures of merit of the PCM cell with operational cycles is electrically characterized. Based on the electrical characterization and published material characterization data, a physical model of an evolving "active region" of the cell is proposed to explain the improvement of the cell parameters with operational cycles. Then, basic understanding is developed on early and erratic retention failure in a statistically significant number of cells in a large array and, electrical characterization and physical modeling is used to explain the mechanism behind the early retention failure.

No description available.

No description available.

No description available.

No description available.

No description available.

No description available.