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1	Test fixture characterization for high-frequency silicon substrate parasitic extraction / Tabalujan, Andrew R. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 72-73). Also available on the World Wide Web. Substrate noise.
2	Automated model parameter extraction for noise coupling analysis in silicon substrates / Peterson, Brett. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 60-62). Also available on the World Wide Web. Substrate noise Mixed signal circuits
3	Substrate noise coupling in ring oscillator-based phase locked loops / Shreeve, Robert. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 43-45). Also available on the World Wide Web. Phase-locked loops. Substrate noise.
4	Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs / Sundaresan, Arathi. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 69-72). Also available on the World Wide Web. Low noise amplifiers. Substrate noise.
5	Suppression of substrate noise in a mixed-signal CMOS intergrated circuit Lim, Wei Tjan (Richard) 29 May 1996 (has links) Substrate switching noise is becoming a concern as integrated circuits get larger and speeds get faster. Mixed-mode integrated circuits are especially affected as the substrate noise interferes with sensitive analog circuits resulting in limited signal to noise ratios. This thesis serves to study the cause of the noise at the point where it is generated to the way it propagates to the analog circuits, and presents several approaches to reduce the switching noise. In addition, it examines the substrate impedance as being a key element to successful and reliable design for low-noise CMOS mixed-signal integrated circuits. Utilizing the substrate lead inductance and current-variable capacitances through the use of guard ring diodes, resonant frequencies which provide a low impedance path to ground are created. These can be tuned to coincide with problematic noise frequency components or to cancel the pin and package resonance, thus suppressing noise and improving reliability. / Graduation date: 1997 Substrate noise
6	Characterization of substrate noise coupling, its impacts and remedies in RF and mixed-signal ICs Helmy, Ahmed. January 2006 (has links) Thesis (Ph. D.)--Ohio State University, 2006. / Full text release at OhioLINK's ETD Center delayed at author's request
7	Computationally efficient substrate noise coupling estimation in lightly doped silicon substrates / Srinivasan, Kavitha. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 80-81). Also available on the World Wide Web.
8	Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits / Hanken, Christopher. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 57-59). Also available on the World Wide Web.
9	Contributions to substrate noise due to supply coupling and pin parasitics Adluri, Sirisha 14 November 2003 (has links) Graduation date: 2004 Integrated circuits -- Noise Switching circuits -- Noise Substrate noise
10	Comparison and impact of substrate noise due to clocked and clockless circuitry / Le, Jim K. January 1900 (has links) Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 53-54). Also available on the World Wide Web.

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