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Context. In the present network inventive world, there is a quick expansion of switches and protocols, which are used to cope up with the increase in customer requirement in the networking. With increasing demand for higher bandwidths and lower latency and to meet these requirements new network paths are introduced. To reduce network load in present switching network, development of new innovative switching is required. These required results can be achieved by Software Define Network or Traditional layer-3 technologies.Objectives. In this thesis, the end to end (e2e) transmission performance of OpenFlow and Layer-3 switches and their dynamic characteristics are investigated using network simulation.Methods. To replicate real life network topology and evaluate e2e transmission performance, a simulation based test-bed is implemented for both OpenFlow switch and layer-3 switch. The test beds are implemented using Network Simulator-3 (NS3). A two-tire network topology is designed with specified components for performance evaluation.Results. The performance metrics like throughput, average delay, simulation time and Packet Delivery Ratio (PDR) are measured, results are analyzed statistically and are compared. The behavior of network traffic in both the topologies are understood using NS-3 and explained further in the thesis.Conclusions. The analytical and statistical results from simulation show that OpenFlow switching performs relatively better than layer-3 switching.

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Switch-Reference (SR) is a phenomenon in which the coreferentiality of two (or more) subjects in a complex sentence is indicated by a morphological device. The purpose of this dissertation is to discuss recent work which deals with SR within the Government and Binding Theory, and propose an alternative analysis to it. The framework I will adopt for such an alternative analysis of SR is Categorial Grammar. A basic notion underlying Categorial Grammar is that an expression is divided into a functor and an argument, and each functor and argument are further divided into a functor and an argument until the division reaches to an undividable element. Given the assumptions that a functor and its argument must be compatible and that a functor has some subcategorization properties, I argue that "Agreement" phenomenon (subsuming agreement and disagreement) can be handled insightfully. Furthermore, I propose that such a treatment of "Agreement" can be extended to SR systems in general if we consider the "same subject" and "different subject" phenomena as cases of agreement and disagreement, respectively. I claim that a composite in which a SR morpheme appears forms a functor which takes another composite as its argument, and that the relation between the functor and its argument and the relation between some parts of the functor and its argument are characterized as "agreement" or "disagreement": The functor and the argument must be compatible as assumed above, and the nature of compatibility (whether "agreement" or "disagreement") is controlled by the subcategorization properties of the SR morpheme associated with the functor (i.e., if "same subject", the relation is agreement, and if "different subject", it is disagreement). By treating SR in this fashion, I intend to provide a unified analysis for apparently different SR systems in three diverse languages, namely, Tairora, Hopi, and Warlpiri.

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Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

With extremely wide bandwidth and good channel properties, optical fibers have brought fast and reliable data transmission to todays data communications. However, to handle heavy traffic flowing through optical physical links, much faster processing speed is required or else congestion can take place at network nodes. Also, to provide people with voice, data and all categories of multimedia services, distinguishing between different data flows is a requirement. To address these router performance, Quality of Service /Class of Service and traffic engineering issues, Multi-Protocol Label Switching (MPLS) was proposed for IP-based Internetworks. In addition, routers flexible in hardware architecture in order to support ever-evolving protocols and services without causing big infrastructure modification or replacement are also desirable. Therefore, reconfigurable hardware implementation of MPLS was proposed in this project to obtain the overall fast processing speed at network nodes. The long-term goal of this project is to develop a reconfigurable MPLS router, which uniquely integrates the best features of operations being conducted in software and in run-time-reconfigurable hardware. The scope of this thesis includes system architecture and service algorithm considerations, Verilog coding and testing for an actual device. The hardware and software co-design technique was used to partition and schedule the protocol code for execution on both a general-purpose processor and stream-based hardware. A novel RPS scheme that is practically easy to build and can realize pipelined packet-by-packet data transfer at each output was proposed to take the place of the traditional crossbar switching. In RPS, packets with variable lengths can be switched intelligently without performing packet segmentation and reassembly. Primary theoretical analysis of queuing issues was discussed and an improved multiple queue service scheduling policy UD-WRR was proposed, which can reduce packet-waiting time without sacrificing the performance. In order to have the tests carried out appropriately, dedicated circuitry for the MPLS functional block to interface a specific MAC chip was implemented as well. The hardware designs for all functions were realized with a single Field Programmable Gate Array (FPGA) device in this project. The main result presented in this thesis was the MPLS function implementation realizing a major part of layer three routing at the reconfigurable hardware level, which advanced a great step towards the goal of building a router that is both fast and flexible.

With extremely wide bandwidth and good channel properties, optical fibers have brought fast and reliable data transmission to todays data communications. However, to handle heavy traffic flowing through optical physical links, much faster processing speed is required or else congestion can take place at network nodes. Also, to provide people with voice, data and all categories of multimedia services, distinguishing between different data flows is a requirement. To address these router performance, Quality of Service /Class of Service and traffic engineering issues, Multi-Protocol Label Switching (MPLS) was proposed for IP-based Internetworks. In addition, routers flexible in hardware architecture in order to support ever-evolving protocols and services without causing big infrastructure modification or replacement are also desirable. Therefore, reconfigurable hardware implementation of MPLS was proposed in this project to obtain the overall fast processing speed at network nodes. The long-term goal of this project is to develop a reconfigurable MPLS router, which uniquely integrates the best features of operations being conducted in software and in run-time-reconfigurable hardware. The scope of this thesis includes system architecture and service algorithm considerations, Verilog coding and testing for an actual device. The hardware and software co-design technique was used to partition and schedule the protocol code for execution on both a general-purpose processor and stream-based hardware. A novel RPS scheme that is practically easy to build and can realize pipelined packet-by-packet data transfer at each output was proposed to take the place of the traditional crossbar switching. In RPS, packets with variable lengths can be switched intelligently without performing packet segmentation and reassembly. Primary theoretical analysis of queuing issues was discussed and an improved multiple queue service scheduling policy UD-WRR was proposed, which can reduce packet-waiting time without sacrificing the performance. In order to have the tests carried out appropriately, dedicated circuitry for the MPLS functional block to interface a specific MAC chip was implemented as well. The hardware designs for all functions were realized with a single Field Programmable Gate Array (FPGA) device in this project. The main result presented in this thesis was the MPLS function implementation realizing a major part of layer three routing at the reconfigurable hardware level, which advanced a great step towards the goal of building a router that is both fast and flexible.

The methods of improving the cache performance are multiform and advanced of nowadays. We are concerned about the cache and TLB utility. To reduce the context switch cost on system, we utilize an address-space switching hardware of ARMS3C2410 processor to realize the fast address switching mechanism. The Fast Context Switch can help to improve cache and TLB utility and performance. Fast Context Switch is a method that can help to improve the cache performance. The key feature of Fast Context Switch is without any cache and TLB flush on process context switching. To implement Fast Context Switch, we address the different processes to different address space by process ID. When context switch occurs, we can just change the working space without the cache and TLB flush. This thesis emphasizes on the performance measure for improvement on the cache and TLB. We use a high dependable microkernel architecture for message passing between processes, this microkernel called MinixARM. Rely on the microkernel, we can more easily understand and analyze the system performance and additional cost of the cache scheme. We provide more complete performance tests by benchmarks, fast context switch can increase the system performance about 65% at most.

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