FPGAs provide parallel computing that is fit for speeding up the computation of a large range of problems. Programming an FPGA involves a complex tool flow for which several CAD tools have been developed. These tools compute solutions to many problems such as packing, placement, and routing, which map a circuit design onto an FPGA. These computations require a great deal of memory, of which the Routing Resource Graph contributes the most of any individual data structure. If the RRGraph could be represented in a more compact manner, performance of the tool flow algorithms may be improved due to an increase in memory caching benefits. This work presents four variations on RRGraph folding which vary in memory usage reduction and runtime, with the most aggressive method reducing the RRGraph size by up to 4x while maintaining similar performance to the original representation.

The open-source community is a valuable resource for many hobbyists and researchers interested in collaborating and contributing towards publicly available tools. In the area of field programmable gate arrays (FPGAs) this is no exception. Contributors seek to reverse-engineer the functions of large proprietary FPGA devices. An interesting challenge for open-source FPGA engineers has been reverse-engineering the operation and bitstreams of digital signal processing (DSP) blocks located in FPGAs. SymbiFlow is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. For SymbiFlow, mapping logical multipliers to DSP blocks and generating DSP block bitstreams has been left unimplemented for the Artix-7 family of FPGAs. This research seeks to rectify this shortcoming by introducing DSP information for the place and route functions into SymbiFlow. By delving into the SymbiFlow architecture definitions and creating functioning FPGA assembly code (FASM) files for Project X-Ray, a bitstream generator for Artix-7, we have been able to determine the desired output of the open-source Versatile Place & Route tool that will generate a working DSP bitstream. We diagnose and implement changes needed throughout the SymbiFlow toolchain, allowing for DSP design bitstreams to be successfully generated with open-source tools.