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As SystemC gains popularity as a System Level Design Language (SLDL) for System-On-Chip (SOC) designs, heterogeneous modelling and efficient simulation become increasingly important. The key in making an SLDL heterogeneous is the facility to express different Models Of Computation (MOC). Currently, all SystemC models employ a Discrete-Event simulation kernel making it difficult to express most MOCs without specific designer guidelines. This often makes it unnatural to express different MOCs in SystemC. For the simulation framework, this sometimes results in unnecessary delta cycles for models away from the Discrete-Event MOC, hindering the simulation performance of the model. Our goal is to extend SystemC's simulation framework to allow for better modelling expressiveness and efficiency for the Synchronous Data Flow (SDF) MOC. The SDF MOC follows a paradigm where the production and consumption rates of data by a function block are known a priori. These systems are common in Digital Signal Processing applications where relative sample rates are specified for every component. Knowledge of these rates enables the use of static scheduling. When compared to dynamic scheduling of SDF models, we experience a noticeable improvement in simulation efficiency. We implement an extension to the SystemC kernel that exploits such static scheduling for SDF models and propose designer style guidelines for modelers to use this extension. The modelling paradigm becomes more natural to SDF which results to better simulation efficiency. We will distribute our implementation to the SystemC community to demonstrate that SystemC can be a heterogeneous SLDL. / Master of Science

The implementation of embedded software applications is a complex process. The complexity arises from the intense time-to-market pressures; power and memory constraints. To deal with this complexity, an idea is to automatically construct the applications based on the high-level abstraction model. Synchronous data flow (SDF) is a high-level model of computation, and is used to model the embedded applications. Formal System Design (ForSyDe), developed by ForSyDe group at KTH Royal Institute of Technology, is a methodology for modeling and designing heterogeneous systems-on-chip. The aim of Formal System Design (ForSyDe) is to automatically generate the detailed software implementation or hardware implementation according to the high-level system specification. Formal System Design (ForSyDe) starts from the high-level system specification and specifies the system model in Haskell language. Synchronous data flow is supported by ForSyDe. ForSyDe IO is an intermediate representation of the high-level system specification. This master thesis focuses on the software synthesis of synchronous data flow models specified in ForSyDe IO, and aims to produce an automatic code generator that can generate software applications in C code for different platforms based on ForSyDe IO. In this project, a software synthesis method for ForSyDe IO was proposed. Then, based on the software synthesis method, a code generator, written in Java and Xtend, was designed. The derived code generator was tested on two examples. The experiment results show that the synchronous data flow models specified in ForSyDe IO are successfully synthesized into C code. The code is in the Github repository https://github.com/Rojods/CInTSyDe.git with MIT license. / Implementeringen av inbäddade mjukvaruapplikationer är en komplex process. Komplexiteten beror på det intensiva trycket på tid-till-marknad; kraft- och minnesbegränsningar. För att hantera denna komplexitet är en idé att applikationerna automatiskt kan konstrueras den högnivåabstraktionsmodellen. Synkront dataflöde (SDF) är en beräkningsmodell på hög nivå som används för att modellera inbäddade applikationer. Formell systemdesign (ForSyDe), utvecklad av ForSyDe-gruppen vid KTH, Kungliga Tekniska Högskolan , är en metodik för modellering och design av heterogena system på chipp. Syftet med formell systemdesign (ForSyDe) är att automatiskt generera den detaljerade mjuk- eller hårdvaruimplementationen enligt systemspecifikationen på hög nivå. Formell systemdesign (ForSyDe) utgår från systemspecifikationen på hög nivå och specificerar systemmodellen på Haskell-språket. Synkront dataflöde stöds av ForSyDe. ForSyDe IO är en mellanrepresentation av systemspecifikationen på hög nivå. Detta examensarbete fokuserar på mjukvarusyntesen av ForSyDe IO och synkront dataflöde, och syftar till att producera ett automatiskt verktyg som kan generera mjukvaruapplikation i C-kod för olika plattformar baserat på ForSyDe IO. I detta projekt föreslås en mjukvarusyntesmetod för ForSyDe IO. Sedan, baserat på mjukvarusyntesmetoden, designas en kodgenerator skriven i Java och Xtend. Den härledda kodgeneratorn testas på två exempel. Experimentresultaten visar att ForSyDe IO framgångsrikt har syntetiserats till C-kod.