The work presented in this thesis aims at validating an original multicriteria performances estimation tool, NESSIE, dedicated to the prediction of performances to accelerate the design of electronic embedded systems. <p><p>This tool has been developed in a previous thesis to cope with the limitations of existing design tools and offers a new solution to face the growing complexity of the current applications and electronic platforms and the multiple constraints they are subjected to. <p><p>More precisely, the goal of the tool is to propose a flexible framework targeting embedded systems in a generic way and enable a fast exploration of the design space based on the estimation of user-defined criteria and a joint hierarchical representation of the application and the platform.<p><p>In this context, the purpose of the thesis is to put the original framework NESSIE to the test to analyze if it is indeed useful and able to solve current design problems. Hence, the dissertation presents :<p><p>- A study of the State-of-the-Art related to the existing design tools. I propose a classification of these tools and compare them based on typical criteria. This substantial survey completes the State-of-the-Art done in the previous work. This study shows that the NESSIE framework offers solutions to the limitations of these tools.<p>- The framework of our original mapping tool and its calculation engine. Through this presentation, I highlight the main ingredients of the tool and explain the implemented methodology.<p>- Two external case studies that have been chosen to validate NESSIE and that are the core of the thesis. These case studies propose two different design problems (a reconfigurable processor, ADRES, applied to a matrix multiplication kernel and a 3D stacking MPSoC problem applied to a video decoder) and show the ability of our tool to target different applications and platforms. <p><p>The validation is performed based on the comparison of a multi-criteria estimation of the performances for a significant amount of solutions, between NESSIE and the external design flow. In particular, I discuss the prediction capability of NESSIE and the accuracy of the estimation. <p><p>-The study is completed, for each case study, by a quantification of the modeling time and the design time in both flows, in order to analyze the gain achieved by our tool used upstream from the classical tool chain compared to the existing design flow alone. <p><p><p>The results showed that NESSIE is able to predict with a high degree of accuracy the solutions that are the best candidates for the design in the lower design flows. Moreover, in both case studies, modeled respectively at a low and higher abstraction level, I obtained a significant gain in the design time. <p><p>However, I also identified limitations that impact the modeling time and could prevent an efficient use of the tool for more complex problems. <p><p>To cope with these issues, I end up by proposing several improvements of the framework and give perspectives to further develop the tool. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished

The work presented in this thesis targets the analysis and implementation of multi-criteria performance prediction methods for System-on-Chips (SoC).<p>These new SoC architectures offer the opportunity to integrate complete heterogeneous systems into a single chip and can be used to design battery powered handhelds, security critical systems, consumer electronics devices, etc. However, this variety in terms of application usually comes with a lot of different performance objectives like power consumption, yield, design cost, production cost, silicon area and many others. These performance requirements are often very difficult to meet together so that SoC design usually relies on making the right design choices and finding the best performance compromises.<p>In parallel with this architectural paradigm shift, new Very Deep Submicron (VDSM) silicon processes have more and more impact on the performances and deeply modify the way a VLSI system is designed even at the first stages of a design flow.<p>In such a context where many new technological and system related variables enter the game, early exploration of the impact of design choices becomes crucial to estimate the performance of the system to design and reduce its time-to-market.<p>In this context, this thesis presents: <p>- A study of state-of-the-art tools and methods used to estimate the performances of VLSI systems and an original classification based on several features and concepts that they use. Based on this comparison, we highlight their weaknesses and lacks to identify new opportunities in performance prediction.<p>- The definition of new concepts to enable the automatic exploration of large design spaces based on flexible performance criteria and degrees of freedom representing design choices.<p>- The implementation of a couple of two new tools of our own:<p>- Nessie, a tool enabling hierarchical representation of an application along with its platform and automatically performs the mapping and the estimation of their performance.<p>-Yeti, a C++ library enabling the defintion and value estimation of closed-formed expressions and table-based relations. It provides the user with input and model sensitivity analysis capability, simulation scripting, run-time building and automatic plotting of the results. Additionally, Yeti can work in standalone mode to provide the user with an independent framework for model estimation and analysis.<p><p>To demonstrate the use and interest of these tools, we provide in this thesis several case studies whose results are discussed and compared with the literature.<p>Using Yeti, we successfully reproduced the results of a model estimating multi-core computation power and extended them thanks to the representation flexibility of our tool.<p>We also built several models from the ground up to help the dimensioning of interconnect links and clock frequency optimization.<p>Thanks to Nessie, we were able to reproduce the NoC power consumption results of an H.264/AVC decoding application running on a multicore platform. These results were then extended to the case of a 3D die stacked architecture and the performance benefits are then discussed.<p>We end up by highlighting the advantages of our technique and discuss future opportunities for performance prediction tools to explore. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished

Ce mémoire traite des systèmes intégrés sur puce (System-on-Chip) à faible consommation d'énergie tels que ceux qui seront utilisés dans les équipements portables de future génération (ordinateurs de poche (PDA), téléphones mobiles). S'agissant d'équipements alimentés par des batteries, la consommation énergétique est un problème critique. <p><p>Ces plateformes contiendront probablement une douzaine de coeurs de processeur et une quantité importante de mémoire embarquée. Une architecture de communication optimisée sera donc nécessaire afin de les interconnecter de manière efficace. De nombreuses architectures de communication ont été proposées dans la littérature: bus partagés, bus pontés, bus segmentés et plus récemment, les réseaux intégrés (NoC).<p><p>Toutefois, à l'exception des bus, la consommation d'énergie des réseaux d'interconnexion intégrés a été largement ignorée pendant longtemps. Ce n'est que très récemment que les premières études sont apparues dans ce domaine.<p><p>Cette thèse présente:<p><p>- Une analyse complète de l'espace de conception des architectures de communication intégrées. Sur base de cet espace de conception et d'un état de l'art détaillé, des techniques jusqu'alors inexplorées ont pu être identifiées et investiguées. <p>- La conception d'environnements de simulation de bas et haut niveaux permettant de réaliser des comparaisons entre différentes architectures de communication en termes de consommation énergétique et de surface.<p>- La conception et la validation d'une architecture de communication intégrée innovante basée sur le multiplexage spatial<p><p>Ce dernier point a pour ambition de démontrer qu'un réseau basé sur le multiplexage spatial (SDM) constitue une alternative intéressante aux réseaux classiques principalement basés sur le multiplexage temporel dans le contexte très spécifique des architectures de communication intégrées.<p><p>Nous démontrerons la validité de la solution proposée à l'aide de campagnes de simulation de haut niveau pour divers types de trafic ainsi que des simulations de plus bas niveau. L'étude concerne successivement la conception de routers SDM, des interfaces réseau et finalement d'un réseau complet. Les avantages et inconvénients d'une telle technique seront discutés en détails. / Doctorat en sciences appliquées / info:eu-repo/semantics/nonPublished