In a multiprocessor system-on-chip (MPSOC), parallel processors are utilized to enhance overall performance. However, the communication between processors and memory modules can affect overall performance significantly. We proposed a software design of communication performance estimation for system synthesis. We designed a hardware simulator of mesh communication architecture of MPSOC. We implemented the simulator of router nodes in SystemC language. An analytical communication performance estimation model can be trained with data measured from communication simulation. It can then be utilized for estimating inter-processor communication performance in an MPSOC.

Made available in DSpace on 2014-06-11T19:30:51Z (GMT). No. of bitstreams: 0 Previous issue date: 2008-02-26Bitstream added on 2014-06-13T19:19:32Z : No. of bitstreams: 1 oliveira_t_dr_ilha.pdf: 1857904 bytes, checksum: 58f64d9e638aa2a1040b97776689687b (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / O objetivo desta tese é o desenvolvimento de uma arquitetura multiprocessada e reconfiguravel que permita a implementação física de sistemas de controle descritos por meio de Redes de Petri coloridas de arcos constantes T-temporizadas e que possuam pro- babilidade de disparo nas transições. A arquitetura pode ser utilizada para implementar sistemas de controle (e n~ao para a avaliacao das propriedades da Rede de Petri), permi- tindo a implementacao física por meio de mapeamento tecnologico diretamente no nível comportamental, sem a necessidade de se utilizar um processo de síntese de alto nível para descrever o sistema em equações booleanas e tabelas de transição de estados. A arquitetura é composta por um arranjo de blocos de configuracao denominados BCERPs, por blocos reconfiguráveis denominados BCGNs e por um sistema de comunicacão, implementado por um conjunto de roteadores. Os blocos BCERPs podem ser configurados para implementar as transições da Rede de Petri e seus respectivos lugares de entrada. Blocos BCGNs são utilizados pelos blocos BCERPs para a geração de numeros pseudo-aleatorios. Estes numeros podem definir a probabilidade de disparo das transições e tambem podem ser usados no processo de resolução de conflito, que ocorre quando uma transição possuir um ou mais lugares de entrada compartilhados com outras transições. O sistema de comunicacão possui uma topologia de grelha, tendo como principal função o roteamento e armazenamento de pacotes entre os blocos de configuração. Os roteadores e blocos de configuração BCERPs e BCGNs foram descritos em VHDL e implementados em FPGAs. / The goal of this thesis is to develop a reconfigurable multiprocessed architecture that allows the physical implementation of systems described by T-timed colored Petri nets with constant arcs having transitions with firing probabilities. The architecture can be used to implement control systems (not to evaluation Petri net properties). With this architecture, physical implementation of systems can be achieved through technology mapping directly from behavioral level, without the need to go through an expensive high level synthesis process to describe the system into boolean equations and state transition tables. The architecture comprises an array of configuration blocks named BCERPs; reconfigurable blocks named BCGNs; and a communication system implemented using a set of routers. BCERP blocks can be configured to implement Petri net transitions as well as the corresponding input places. BCGN blocks are used by BCERPs for pseudo random number generation. These numbers can define transitions firing probabilities. They can also be used for conflit resolution, which happens when two or more transitions share one or more input places. The communication system presents a grid topology. Its main functions are packet storage and routing among configuration blocks. The routers, BCGNs and BCERPs configuration blocks were described in VHDL and implemented in FPGAs.

Orientador: Norian Marranghello / Banca: Aledir Silveira Pereira / Banca: Alexandre Cesar Rodrigues da Silva / Banca: Furio Damiani / Banca: Paulo Romero Martins Maciel / Resumo: O objetivo desta tese é o desenvolvimento de uma arquitetura multiprocessada e reconfiguravel que permita a implementação física de sistemas de controle descritos por meio de Redes de Petri coloridas de arcos constantes T-temporizadas e que possuam pro- babilidade de disparo nas transições. A arquitetura pode ser utilizada para implementar sistemas de controle (e n~ao para a avaliacao das propriedades da Rede de Petri), permi- tindo a implementacao física por meio de mapeamento tecnologico diretamente no nível comportamental, sem a necessidade de se utilizar um processo de síntese de alto nível para descrever o sistema em equações booleanas e tabelas de transição de estados. A arquitetura é composta por um arranjo de blocos de configuracao denominados BCERPs, por blocos reconfiguráveis denominados BCGNs e por um sistema de comunicacão, implementado por um conjunto de roteadores. Os blocos BCERPs podem ser configurados para implementar as transições da Rede de Petri e seus respectivos lugares de entrada. Blocos BCGNs são utilizados pelos blocos BCERPs para a geração de numeros pseudo-aleatorios. Estes numeros podem definir a probabilidade de disparo das transições e tambem podem ser usados no processo de resolução de conflito, que ocorre quando uma transição possuir um ou mais lugares de entrada compartilhados com outras transições. O sistema de comunicacão possui uma topologia de grelha, tendo como principal função o roteamento e armazenamento de pacotes entre os blocos de configuração. Os roteadores e blocos de configuração BCERPs e BCGNs foram descritos em VHDL e implementados em FPGAs. / Abstract: The goal of this thesis is to develop a reconfigurable multiprocessed architecture that allows the physical implementation of systems described by T-timed colored Petri nets with constant arcs having transitions with firing probabilities. The architecture can be used to implement control systems (not to evaluation Petri net properties). With this architecture, physical implementation of systems can be achieved through technology mapping directly from behavioral level, without the need to go through an expensive high level synthesis process to describe the system into boolean equations and state transition tables. The architecture comprises an array of configuration blocks named BCERPs; reconfigurable blocks named BCGNs; and a communication system implemented using a set of routers. BCERP blocks can be configured to implement Petri net transitions as well as the corresponding input places. BCGN blocks are used by BCERPs for pseudo random number generation. These numbers can define transitions firing probabilities. They can also be used for conflit resolution, which happens when two or more transitions share one or more input places. The communication system presents a grid topology. Its main functions are packet storage and routing among configuration blocks. The routers, BCGNs and BCERPs configuration blocks were described in VHDL and implemented in FPGAs. / Doutor

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The transistor count for todays VLSI technology reaches 40 million transistors on one chip. In order to successfully design a system with such complexity, new computer-aided design (CAD) tools are needed. This dissertation shows approaches for coping with the problem of increasing complexity of VLSI design in three aspects: 1) capturing a higher level of abstraction, 2) using a new target architecture, and 3) using a new optimization technique. The advantage of working at a higher level of abstraction is that the number of objects that designers have to manipulate is reduced so that more complex systems can be delivered in shorter periods of time. The functions that can be used to capture higher levels of abstraction are surveyed and categorized into an is-a hierarchy. A partitioned-bus architecture that consists of complex functional units used to realize complex functions is proposed. The issues of synthesizing the complex functions to the partitioned-bus architecture are addressed. These issues are focused on the functional partitioning problem which is a known NP-complete problem. Algorithms used to optimize several metrics that affect the solution qualities of functional partitioning are presented. The metrics include communication buffer size, register file size, system delay, the number of buses, the number of links, and the number of multiplexers. These metrics are used to form a cost function, which is utilized by the Problem Space Genetic Partitioning algorithm (PSGP) to search for a good solution. Test cases with known optimal solutions are used to evaluate the solution qualities that PSGP can attain under run time and memory space constraints. The experimental results show that PSGP can reach an average about 87% of the optima for two-way partitioning. Another study also shows that PSGP outperforms the widely used Simulated Annealing algorithm. / Ph. D.

No / An adaptive iterative learning control approach is proposed for a class of single-input single-output uncertain nonlinear systems with completely unknown control gain. Unlike the ordinary iterative learning controls that require some preconditions on the learning gain to stabilize the dynamic systems, the adaptive iterative learning control achieves the convergence through a learning gain in a Nussbaum-type function for the unknown control gain estimation. This paper shows that all tracking errors along a desired trajectory in a finite time interval can converge into any given precision through repetitive tracking. Simulations are carried out to show the validity of the proposed control method.

No / A multivariable model of an automotive gas turbine, obtained from the linearized system equations is investigated. To facilitate vehicle speed changes, whilst protecting the system against thermal damage, control of the power turbine inlet gas temperature and gas generator speed is proposed by feedback regulation. Fuel flow and the power turbine nozzle area variations are the selected, manipulatable inputs. Owing to the limited control energy available for regulation purposes a multivariable, optimum, minimum control effort strategy is employed in the inner loop controller design study. Simulated, open and closed loop system responses are presented for purposes of comparison. Significant improvements in the transient response interaction reaction times and low steady state output interaction achieved using passive compensation and output feedback alone. Simplification of the closed loop configuration is proposed in the final implementation without performance penalties.