Jusqu'à présent, le test de circuits intégrés et des systèmes au niveau wafer est basé sur un contact physique entre l'équipement de test et les circuits sur le wafer. Cette méthode basée sur le contact est limitée par plusieurs facteurs, tels que le nombre de circuits testés en parallèle, la réduction de la taille et de l'espacement entre les plots de contact, le nombre de contact avant que les plots soient endommagés, le coût des opérations de test, entre autres. Pour résoudre ces problèmes, nous proposons une nouvelle approche de test basée sur la communication sans fil entre le testeur et les circuits à tester (DUT). Pour cela, un Wireless Test Control Bloc (WTCB) est ajouté à chaque DUT sur le wafer comme une interface sans fil entre le testeur et les structures de test internes du DUT. Ce WTCB intègre une pile protocolaire de communication pour gérer la communication avec le testeur, et un Test Control Bloc (TCB) pour gérer l'application de test au niveau DUT. Profitant d'une transmission sans fil, le testeur peut diffuser les données de test à tous les DUT sur le wafer , maximisant le test simultané et réduisant donc le temps de test. En outre, notre architecture de WTCB permet une comparaison locale de la réponse de DUT avec la réponse correcte attendue par le testeur. En effectuant cette comparaison dans le WTCB du DUT, le testeur recueille de chaque DUT 1 seul bit comme résultat de la comparaison, au lieu d'une réponse complète, conduisant à un test sans fil plus rapide qui réduit le temps d'essai. Le WTCB a été mis en oeuvre sur FPGA, et une épreuve de test sans fil d'un circuit réel a été réalisée, prouvant la conception efficace de notre WTCB, et soulignant le potentiel de notre méthode de test sans fil, où elle peut être étendue et utilisée pour des applications de test in situ à distance. / So far, the test of integrated circuits and systems at wafer level relies on a physical contact between the test equipment and the devices under test on the wafer. This contact-based method is limited by several factors, such as the number of devices tested in parallel, the reduction of the size and the pitch of the bond pads, the number of touchdowns before bond pads are damaged, the cost of the test operations, among others. To solve these issues, we propose a novel test approach and architecture based on wireless communication between the tester and the devices under test (DUT). For that, a Wireless Test Control Block (WTCB) is added to every DUT on the wafer as a wireless interface between the tester and the internal test structures of the DUT. This WTCB embeds a communication protocol stack to manage the communication with the tester, and a Test Control Block to manage the test application at DUT level. Taking advantage of a wireless transmission, the tester can broadcast the test data to all DUT on the wafer in one path, maximizing the concurrent test, and reducing therefore the test time. Moreover, our WTCB architecture allows a local comparison of the DUT response with the correct response expected by the tester. By performing this comparison in the WTCB of the DUT, the tester collects from every DUT its 1-bit comparison result instead of a complete response, leading to a faster wireless test and extremely reduced test time. The WTCB has been implemented on FPGA, and a successful wireless test of a real circuit was performed, proving the efficient design of our WTCB, and highlighting the potential of our wireless test method, where it can be extended and used to perform a remote in-situ test.

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, and hence there exist many difficult engineering challenges, most notably in power management, noise isolation, and intra and inter-chip communication. Significant research effort spanning many decades has been expended on traditional VLSI integration technologies, encompassing process, circuit and architectural issues to tackle these problems. Recently however, three- dimensional (3-D) integration has emerged as a leading contender in the challenge to meet performance, heterogeneous integration, cost, and size demands through this decade and beyond. Through silicon via (TSV) based 3-D wafer-level integration is an emerging vertical interconnect methodology that is used to route the signal and power supply links through all chips in the stack vertically. Delay and signal integrity (SI) calculation for signal propagation through TSVs is a critical analysis step in the physical design of such systems. In order to reduce design time and mirror well established practices, it is desirable to carry this out in two stages, with the physical structures being modelled by parasitic parameters in equivalent circuits, and subsequent analysis of the equivalent circuits for the desired metric. This thesis addresses both these issues. Parasitic parameter extraction is carried out using a field solver to explore trends in typical technologies to gain an insight into the variation of resistive, capacitive and inductive parasitics including coupling effects. A set of novel closed-form equations are proposed for TSV parasitics in terms of physical dimensions and material properties, allowing the electrical modelling of TSV bundles without the need for computationally expensive field-solvers. Suitable equivalent circuits including capacitive and inductive coupling are derived, and comparisons with field solver provided values are used to show the accuracy of the proposed parasitic parameter models for the purpose of performance and SI analysis. The deep submicron era saw the interconnection delay rather than the gate delay become the major bottleneck in modern digital design. The nature of this problem in 3-D circuits is studied in detail in this thesis. The ubiquitous technique of repeater insertion for reducing propagation delay and signal degradation is examined for TSVs, and suitable strategies and analysis techniques are proposed. Further, a minimal power smart repeater suitable for global on-chip interconnects, which has the potential to reduce power consumption by as much as 20% with respect to a traditional inverter is proposed. A modeling and analysis methodology is also proposed, that makes the smart repeater easier to amalgamate in CAD flows at different levels of hierarchy from initial signal planning to detailed place and route when compared to alternatives proposed in the literature. Finally, the topic of system-level performance estimation for massively integrated systems is discussed. As designers are presented with an extra spatial dimension in 3-D integration, the complexity of the layout and the architectural trade-offs also increase. Therefore, to obtain a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. This thesis presents a cohesive analysis of the technological, cost, and performance trade-offs for digital and mixed-mode systems, outlining the choices available at different points in the design and their ramifications / QC 20100916

System on Chip (SoC) and System in Package (SiP) are two electronic technologies that involve integrating multiple functionalities onto a single platform. When the platform is a single wafer, as in SOC, it requires the ability to deposit various materials that enable the different functions on to an underlying substrate that can host the electronic circuitry. Transition metal oxides which have a wide range of properties are ideal candidates for the functional material. Si wafer on which micro-electronics technology is widely commercialized is the ideal host platform. Integrating oxides with Si, generally in the form of thin films as required by microelectronics technology, is however a challenge. It starts with the fact that the properties of crystalline oxides to be exploited in performing various functions are direction dependent. Thus, thin films of these oxides need to be deposited on Si in certain crystallographic orientations. Even if a suitably oriented Si wafer surface were available, it does not always provide for epitaxial growth a critical requirement for controlling the crystalline orientation of thin films. This is because Si surface is covered by an amorphous oxide of Si (SiOx). Thus, during growth of the functional oxide, an ambience in which the Si itself will not oxidize needs to be provided. In addition, during thin film growth on either Si or SiOx surface stresses are generated from various sources. Stress and its relaxation are also associated with the formation and evolution of defects. Both, stress and defects need to be managed in order to harness their beneficial effects and prevent detrimental ones. Given the requirement of SoC technology and the problem associated, the research work reported in this thesis was hence concerned with the precise controlling the stress and microstructure in oxide thin films deposited on Si substrates. In order to do so a versatile, ultra high vacuum (UHV) thin film with a base pressure of 10-9 Torr was designed and built as part of this study. The chamber is capable of depositing films by both sputtering (RF & DC) and pulsed laser ablation (PLD). The system has been designed to include an optical curvature measurement tool that enabled real-time stress measurement during growth. Doped zirconia, ZrO2, was chosen as the first oxide to be deposited, as it is among the few oxides that is more stable than SiOx. It is hence used as a buffer layer. It is shown in this thesis that a change in the growth rate at nucleation can lead to (100) or (111) textured films. These two are among the most commonly preferred orientation. Following nucleation a change in growth rate does not affect orientation but affects stress. Thus, independent selection of texture and stress is demonstrated in YSZ thin films on Si. A quantitative model based on the adatom motion on the growth surface and the anisotropic growth rates of the two orientations is used to explain these observations. This study was then subsequent extended to the growth on platinized Si another commonly used Si platform.. A knowledge of the stress and microstructure tailoring in cubic zirconia on Si was then extended to look at the effect of stress on electrical properties of zirconia on germanium for high-k dielectric applications. Ge channels are expected to play a key role in next generation n-MOS technology. Development of high-k dielectrics for channel control is hence essential. Interesting stress and property relations were analyzed in ZrO2/Ge. Stress and texture in pulsed laser deposited (PLD) oxides on silicon and SrTiO3 were studied. It is shown in this thesis that stress tuning is critical to achieve the highest possible dielectric constant. The effect of stress on dielectric constant is due to two reasons. The first one is an indirect effect involving the effect of stress on phase stability. The second one is the direct effect involving interatomic distance. By stress control an equivalent oxide thickness (EOT) of 0.8 nm was achieved in sputter deposited ZrO2/Ge films at 5 nm thickness. This is among the best reported till date. Finally, the effect of growth parameters and deposition geometry on the microstructural and stress evolution during deposition of SrTiO3 on Si and BaTiO3 on SrTiO3 by pulsed laser deposition is the same chamber is described.