München, Techn. Universiẗat, Diss., 2003.

München, Techn. University, Diss., 2003.

Efforts to increase productivity, reduce time to market, reduce costs and desire for increased functionality on a chip are driving semiconductor companies to consider SoC (System-on-a-chip) design. SoC offers the additional benefit of improving performance and design freedom. SoC designs are smaller, energy efficient and cheaper than the multi-chip solutions. Silicon manufacturing technology has improved to an extent where one can create a reliable chip with millions of transistors. Design of these complex systems, on the other hand, is taking longer and is much costlier even when the technology allows integration of the million transistor chips. Keeping these design costs low and reducing development cycle time is vital for any chip design company. Hence, companies need to delicately balance the design costs versus benefits for SoC design. Design turn-around time (TAT) even for large complex designs has been significantly improved by EDA tools despite the complexity added by the ever shrinking device geometries. However, other non technical issues and external dependencies in SoC design such as working with multi-disciplinary design teams, external IP (Intellectual Property) vendors, Electronic Design Automation (EDA) tool vendors and IP protection issues increase the risk of missing project goals and timeline. This paper will address both the technical and non-technical issues that arise when moving to SoC design and provide recommendations on how to address some of the non-technical issues involved. / text

Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be considered to increase the processing speed of the system (due to overheating and other constraints), the development of multiprocessors on a single chip has stepped up to meet the demand. One approach has been to design and develop a multiprocessing platform to handle a large set of homogeneous applications. However, this development has been slow due to the intractable design space, which results when both the hardware and software are required to be adjustable to meet the needs of the dissimilar applications. A different approach has been to limit the number of targeted applications to be similar in some sense. By limiting the number of targeted applications to a cohesive set, the design space can become manageable. This thesis proposes a framework for a multiprocessing system-on-chip (MPSoC), consisting of a cohesive hardware and software architecture intended specifically for problems that are stream-oriented (e.g., video streaming). The framework allows the hardware and software to be customized to fit a specific application within the cohesive set, while narrowing the design space to a manageable set of design parameters. In addition, this thesis designs and develops an analytic model, using a discrete-time Markov chain, to measure the performance of an MPSoC framework implementation when the number of concurrent processing elements is varied. Finally, a chaotic simulated annealing algorithm was developed to determine an optimal mapping and scheduling of tasks to processing elements within the MPSoC.

Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be considered to increase the processing speed of the system (due to overheating and other constraints), the development of multiprocessors on a single chip has stepped up to meet the demand. One approach has been to design and develop a multiprocessing platform to handle a large set of homogeneous applications. However, this development has been slow due to the intractable design space, which results when both the hardware and software are required to be adjustable to meet the needs of the dissimilar applications. A different approach has been to limit the number of targeted applications to be similar in some sense. By limiting the number of targeted applications to a cohesive set, the design space can become manageable. This thesis proposes a framework for a multiprocessing system-on-chip (MPSoC), consisting of a cohesive hardware and software architecture intended specifically for problems that are stream-oriented (e.g., video streaming). The framework allows the hardware and software to be customized to fit a specific application within the cohesive set, while narrowing the design space to a manageable set of design parameters. In addition, this thesis designs and develops an analytic model, using a discrete-time Markov chain, to measure the performance of an MPSoC framework implementation when the number of concurrent processing elements is varied. Finally, a chaotic simulated annealing algorithm was developed to determine an optimal mapping and scheduling of tasks to processing elements within the MPSoC.

Techn. Univ., Diss.--Ilmenau, 2006.

<p>In this report the two-tone PLL circuit intended for on-chip test of RF blocks is presented. The primary application is the third order intermodulation test (TOI), vital for RF front-ends. If the spectral analysis can also be completed by DSP available on the chip or on board, it provides a built in self-test (BiST) which can replace costly test instrumentation (ATE). The advantage of the designed two-tone PLL is that it practically prevents the locking effect while keeping the two oscillation frequencies close. Also by careful design the possible intermodulation distortion of the two-tone stimulus can be avoided.</p><p>The two-tone PLL has been designed and verified at the system level using Verilog-A models in Cadence ^TM.Besides, two building blocks of the PLL were implemented at the circuit level in 90nm CMOS technology. The obtained results are promising in terms of a practical two-tone BiST implementation.</p>

<p>This project targets the problems with design and implementation of Single Instruction </p><p>Multiple Data (SIMD) architectures in System-on-Chip (SoC), with the goal to construct </p><p>a reconfigurable framework in VHDL to ease this process. The resulting framework should </p><p>be implemented on an FPGA and its usability tested. The main parts of a SIMD archi- </p><p>tecture was identified to be the Control Unit (CU), the Processing Elements (PE) and </p><p>the Interconnection Network (ICN), and a framework was constructed with these parts </p><p>as the main building blocks. The constructed framework is reconfigurable in data width, </p><p>memory size, number of PEs, topology and instruction set. To test ease of use and per- </p><p>formance of the system a FIR-filter application was implemented. The scalability of the </p><p>system and its different parts has been measured and comparisons are illustrated.</p>

This project targets the problems with design and implementation of Single Instruction Multiple Data (SIMD) architectures in System-on-Chip (SoC), with the goal to construct a reconfigurable framework in VHDL to ease this process. The resulting framework should be implemented on an FPGA and its usability tested. The main parts of a SIMD archi- tecture was identified to be the Control Unit (CU), the Processing Elements (PE) and the Interconnection Network (ICN), and a framework was constructed with these parts as the main building blocks. The constructed framework is reconfigurable in data width, memory size, number of PEs, topology and instruction set. To test ease of use and per- formance of the system a FIR-filter application was implemented. The scalability of the system and its different parts has been measured and comparisons are illustrated.

This master work of the main subject: Developing and analysis of peripheral serial interface microcontroller RISC8 that is similar to PIC 16C57, goes about all phases of developing microcircuits. There are analyzed ways of the developing system on chip, described hardware description languages. The first phase is to develop and model a code with one of HDL (hardware description languages) like a Verilog. For that reason are used such developing tools as Cadence LDV-5.1, that is used for compiling, elaborating and simulating of the design with graphical interface. The second phase - synthesis is done using products of Synopsys Company such a design analyzer. All phases presented in the manner like a sources, all processes, what have to be done, are described and shown with tables, pictures and other graphical tools. All results described in the same manner. All files presented electronically in compact disc, like source files, .log files, databases and other results. The last chapter of the work describes the result of synthesis in the manner of synthesis constructs comparing two languages: Verilog and SystemC.