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Automatic generation of instruction sequences for software-based self-test of processors and systems-on-a-chipGurumurthy, Sankaranarayanan. January 1900 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.
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Performance evaluation of wireless Networks on ChipChang, Jyun-Lyang. January 2009 (has links) (PDF)
Thesis (M.S. in electrical engineering)--Washington State University, May 2009. / Title from PDF title page (viewed on July 21, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).
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Evaluating hardware/software partitioning and an embedded Linux port of the Virtex-II pro development systemLin, Hsiang-Ling Jamie. January 2006 (has links) (PDF)
Thesis (M.S. in computer engineering)--Washington State University, May 2006. / Includes bibliographical references (p. 63-64).
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Performance evaluation of fault tolerant methodologies for network on chip architectureZhu, Haibo, January 2007 (has links) (PDF)
Thesis (M.S. in electrical engineering)--Washington State University, August 2007. / Includes bibliographical references (p. 57-59).
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On-chip calibration and compensation techniques for wireless SoCs /Bashir, Imran, January 2008 (has links)
Thesis (M.S.)--University of Texas at Dallas, 2008. / Includes vita. Includes bibliographical references (leaves 148-150)
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Scalable System-on-Chip DesignMantovani, Paolo January 2017 (has links)
The crisis of technology scaling led the industry of semiconductors towards the adoption of disruptive technologies and innovations to sustain the evolution of microprocessors and keep under control the timing of the design cycle. Multi-core and many-core architectures sought more energy-efficient computation by replacing a power-hungry processor with multiple simpler cores exploiting parallelism. Multi-core processors alone, however, turned out to be insufficient to sustain the ever growing demand for energy and power-efficient computation without compromising performance. Therefore, designers were pushed to drift from homogeneous architectures towards more complex heterogeneous systems that employ the large number of available transistors to incorporate a combination of customized energy-efficient accelerators, along with the general-purpose processor cores. Meanwhile, enhancements in manufacturing processes allowed designers to move a variety of peripheral components and analog devices into the chip. This paradigm shift defined the concept of {\em system-on-chip} (SoC) as a single-chip design that integrates several heterogeneous components. The rise of SoCs corresponds to a rapid decrease of the opportunity cost for integrating accelerators. In fact, on one hand, employing more transistors for powerful cores is not feasible anymore, because transistors cannot be active all at once within reasonable power budgets. On the other hand, increasing the number of homogeneous cores incurs more and more diminishing returns. The availability of cost effective silicon area for specialized hardware creates an opportunity to enter the market of semiconductors for new small players: engineers from several different scientific areas can develop competitive algorithms suitable for acceleration for domain-specific applications, such as multimedia systems, self-driving vehicles, robotics, and more. However, turning these algorithms into SoC components, referred to as {\em intellectual property}, still requires expert hardware designers who are typically not familiar with the specific domain of the target application. Furthermore, heterogeneity makes SoC design and programming much more difficult, especially because of the challenges of the integration process. This is a fine art in the hands of few expert engineers who understand system-level trade-offs, know how to design good hardware, how to handle memory and power management, how to shape and balance the traffic over an interconnect, and are able to deal with many different hardware-software interfaces. Designers need solutions enabling them to build scalable and heterogeneous SoCs. My thesis is that {\em the key to scalable SoC designs is a regular and flexible architecture that hides the complexity of heterogeneous integration from designers, while helping them focus on the important aspects of domain-specific applications through a companion system-level design methodology.} I open a path towards this goal by proposing an architecture that mitigates heterogeneity with regularity and addresses the challenges of heterogeneous component integration by implementing a set of {\em platform services}. These are hardware and software interfaces that from a system-level viewpoint give the illusion of working with a homogeneous SoC, thus making it easier to reuse accelerators and port applications across different designs, each with its own target workload and cost-performance trade-off point. A companion system-level design methodology exploits the regularity of the architecture to guide designers in implementing their intellectual property and enables an extensive design-space exploration across multiple levels of abstraction. Throughout the dissertation, I present a fully automated flow to deploy heterogeneous SoCs on single or multiple field-programmable-gate-array devices. The flow provides non-expert designers with a set of knobs for tuning system-level features based on the given mix of accelerators that they have integrated. Many contributions of my dissertation have already influenced other research projects as well as the content of an advanced course for graduate and senior undergraduate students, which aims to form a new generation of system-level designers. These new professionals need not to be circuit or register-transfer level design experts, and not even gurus of operating systems. Instead, they are trained to design efficient intellectual property by considering system-level trade-offs, while the architecture and the methodology that I describe in this dissertation empower them to integrate their components into an SoC. Finally, with the open-source release of the entire infrastructure, including the SoC-deployment flow and the software stack, I hope I will be able to inspire other research groups and help them implement ideas that further reduce the cost and design-time of future heterogeneous systems.
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Multiple clock domain synchronization for network on chipsSarkar, Souradip, January 2007 (has links) (PDF)
Thesis (M.S. in computer engineering)--Washington State University, December 2007. / Includes bibliographical references (p. 54-58).
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Low power scan testing and test data compressionLee, Jinkyu, January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.
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Systems-on-a-chip testing using an embedded microprocessorHwang, Sungbae 28 August 2008 (has links)
Not available / text
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Smart microplates: integration of photodiode within micromachined silicon pyramidal cavity for detecting chemiluminescent reactions and methodology for passive RFID-type readout / Integration of photodiode within micromachined silicon pyramidal cavity for detecting chemiluminescent reactions and methodology for passive RFID-type readoutPark, Yoon Sok, 1977- 28 August 2008 (has links)
Since the late 1990s our group has been working with groups in chemistry department at the University of Texas at Austin on a project referred as "Electronic Taste Chip," a MicroElectroMechanical System (MEMS) based miniaturized microfluidic chemical sensor with multianalyte detection capabilities. By integrating optical detection mechanism directly onto the silicon chip a cost effective, compact, and portable sensor can be realized enabling use of these chips out of conventional laboratory environment. Addition to the integration a noble approach of accessing a photodiode with non-contact powerless RFID type readout is presented. By doing so a packaged photodiode can be interrogated without direct electrical contact, enhancing the portability even further for a sensor operated in aqueous medium. First background information regarding the project as well as design and integration criteria is presented followed by demonstration of non-contact RFID-type readout of a photodiode. Detailed discussion on the development of process integration scheme is discussed along with the measurements verifying the performance of the fabricated photodiode. During this investigation normally overlooked design criteria of collection efficiency, the effect of how a target element is to be delivered to a detection mechanism on the overall performance of the sensor, is addressed and discussed.
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