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Performance modelling and high performance buffer design for the system with network on chipLiu, Jin, January 2007 (has links) (PDF)
Thesis (Ph. D.)--Washington State University, December 2007. / Includes bibliographical references (p. 107-112).
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Automating layout of reconfigurable subsystems for systems-on-a-chip /Phillips, Shawn A. January 2004 (has links)
Thesis (Ph. D.)--University of Washington, 2004. / Vita. Includes bibliographical references (leaves 141-147).
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Built-in self test for regular structure embedded cores in system-on-chipGarimella, Srinivas Murthy, Stroud, Charles E. January 2005 (has links) (PDF)
Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references (p.91-96).
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Analog/RF VLSI layout generation : layout retargeting via symbolic template /Jangkrajarng, Nuttorn. January 2006 (has links)
Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 97-102).
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