No description available.

No description available.

Thesis (M.S.)--Naval Postgraduate School, 2002. / Thesis advisor(s): Donald R. Eaton, Kenneth, H. Doerr. Includes bibliographical references (p. 67-69). Also available online.

No description available.

No description available.

It is generally accepted that transient faults are a major cause of failure in micro processor systems. Industrial controllers with embedded microprocessors are particularly at risk from this type of failure because their working environments are prone to transient disturbances which can generate transient faults. In order to improve the reliability of processor systems for industrial applications within a limited budget, fault tolerant techniques for uniprocessors are implemented. These techniques aim to identify characteristics of processor operation which are attributed to erroneous behaviour. Once detection is achieved, a programme of restoration activity can be initiated. This thesis initially develops a previous model of erroneous microprocessor behaviour from which characteristics particular to mal-operation are identified. A new technique is proposed, based on software implemented fault tolerance which, by recognizing a particular behavioural characteristic, facilitates the self-detection of erroneous execution. The technique involves inserting detection mechanisms into the target software. This can be quite a complex process and so a prototype software tool called Post-programming Automated Recovery UTility (PARUT) is developed to automate the technique's application. The utility can be used to apply the proposed behavioural fault tolerant technique for a selection of target processors. Fault injection and emulation experiments assess the effectiveness of the proposed fault tolerant technique for three application programs implemented on an 8, 16, and 32- bit processors respectively. The modified application programs are shown to have an improved detection capability and hence reliability when the proposed fault tolerant technique is applied. General assessment of the technique cannot be made, however, because its effectiveness is application specific. The thesis concludes by considering methods of generating non-hazardous application programs at the compilation stage, and design features for incorporation into the architecture of a microprocessor which inherently reduce the hazard, and increase the detection capability of the target software. Particular suggestions are made to add a 'PARUT' phase to the translation process, and to orientate microprocessor design towards the instruction opcode map.

Lu Guowei. / "January 2005." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

This thesis describes the development of a computer-aided fault tree synthesis package for application in the process industries. It builds on the previous research work carried out in the Plant Engineering Group at Loughborough University. The emphasis has been put on describing the underlying methodology as opposed to the actual computer programs. The methodology described was developed by modelling a number of "real" systems, which had already been analysed using manual fault tree construction techniques by British Gas plc. Additionally a number of standard examples from the literature were utilised, as well as a large number of contrived examples to fully evaluate the package. The problems encountered and their solution are described. The culmination of this project was the implementation of the computer package at the Midlands Research Station of British Gas plc. It is not intended that the package should replace the fault tree expert. It should rather be viewed as a tool to facilitate the work of the process engineer, particularly during the design phase. This should enable the evaluation of many more options, which would otherwise have been proved prohibitive by the effort required to manually synthesise the fault trees.

Thesis (M.S.)--State University of New York at Binghamton, Industrial and Systems Engineering Department, 2006. / Includes bibliographical references.

Project report (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Abstract. Includes bibliographical references (leaves 72-75). Also available via the Internet.