The scaling of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) has continued for over four decades, providing device performance gains and considerable economic benefits. However, continuing this scaling trend is being impeded by the increase in dissipated power. Considering the exponential increase of the number of transistors per unit area in high speed processors, the power dissipation has now become the major challenge for device scaling, and has led to tremendous research activity to mitigate this issue, and thereby extend device scaling limits. In such efforts, non-planar device structures, high mobility channel materials, and devices operating under different physics have been extensively investigated. Non-planar device geometries reduce short-channel effects by enhancing the electrostatic control over the channel. The devices using high mobility channel materials such as germanium (Ge), SiGe, and III-V can outperform Si MOSFETs in terms of switching speed. Tunneling field-effect transistors use interband tunneling of carriers rather than thermal emission, and can potentially realize low power devices by achieving subthreshold swings below the thermal limit of 60 mV/dec at room temperature. In this work, we examine two device options which can potentially provide high switching speed combined with reduced power, namely germanium nanowire (NW) field-effect transistors (FETs) and tunneling field-effect transistors (TFETs). The devices use germanium (Ge) – silicon-germanium (Si[subscript x]Ge[subscript 1-x]) core-shell nanowires (NWs) as channel material for the realization of the devices, synthesized using a 'bottom-up' growth process. The device design and material choice are motivated by enhanced electrostatic control in the cylindrical geometry, high hole mobility, and lower bandgap by comparison to Si. We employ low energy ion implantation of boron and phosphorous to realize highly doped contact regions, which in turn provide efficient carrier injection. Our Ge-Si[subscript x]Ge[subscript 1-x]­ core-shell NW FETs and NW TFETs were fabricated using a conventional CMOS process and their electrical properties were systematically characterized. In addition, TCAD (Technology computer-aided design) simulation is also employed for the analysis of the devices. / text

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D.

The performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over three decades. As Si complementary metal-oxide-semiconductor (CMOS) scaling is approaching the physical and optical limits, the emerging technology involves new materials for the gate dielectrics and the channels as well as innovative structures. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Hence, there have been tremendous research activities to explore the prospects of III-V materials for CMOS applications. Nevertheless, the key challenges for III-V MOSFETs with high-[kappa] oxides such as the lack of high quality, thermodynamically stable insulators that passivate the gate oxide/III-V interface still hinder the development of III-V MOS devices. The main focus of this dissertation is to develop the proper processes and structures for III-V MOS devices that result in good interface quality and high device performance. Firstly, fabrication processes and device structures of surface channel MOSFETs were investigated. The interface quality of In[subscript 0.53]Ga[subscript 0.47]As MOS devices was improved by developing the gate-last process with more than five times lower interface trap density (D[subscript it]) compared to the ones with the gate-first process. Furthermore, the optimum substrate structure was identified for inversion-type In[subscript 0.53]Ga[subscript 0.47]As MOSFETs by investigating the effects of channel doping concentration and thickness on device performance. With the proper process and channel structures, the first inversion-type enhancement-mode In[subscript 0.53]Ga[subscript 0.47]As MOSFETs with equivalent oxide thickness (EOT) of ~10 Å using atomic layer deposited (ALD) HfO₂ gate dielectric were demonstrated. The second part of the study focuses on buried channel InGaAs MOSFETs. Buried channel InGaAs MOSFETs were fabricated to improve the channel mobility using various barriers schemes such as single InP barrier with different thicknesses and InP/InAlAs double-barrier. The impacts of different high-[kappa] dielectrics were also evaluated. It has been found that the key factors enabling mobility improvement at both peak and high-field mobility in In[subscript 0.7]Ga[subscript 0.3]As quantum-well MOSFETs with InP/InAlAs barrier-layers are 1) the epitaxial InP/InAlAs double-barrier confining carriers in the quantum-well channel and 2) good InP/Al₂O₃/HfO₂ interface with small EOT. Record high channel mobility was achieved and subthreshold swing (SS) was greatly improved. Finally, InGaAs tunneling field-effect-transistors (TFETs), which are considered as the next-generation green transistors with ultra-low power consumption, were demonstrated with more than two times higher on-current while maintaining much smaller SS compared to the reported results. The improvements are believed to be due to using the In[subscript 0.7]Ga[subscript 0.3]As tunneling junction with a smaller bandgap and ALD HfO₂ gate dielectric with a smaller EOT. / text

Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scalinginsub-10 nm region, new one(1D) and two dimensional(2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. In the first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moore’s law devices also demands the SOI body thickness, TSi0 which is essentially very challenging task in nano-device engineering. To overcome this circumstance, two dimensional crystals in atomically thin layered materials have found great attention for future nanolectronics device applications. Graphene, one layer of Graphite, is such 2D materials which have found potentiality in high speed nanoelectronics applications due to its several unique electronic properties. However, the zero band gap in pure Graphene makes it limited in switching device or transistor applications. Thus, opening and tailoring a band gap has become a highly pursued topic in recent graphene research. The second part of this work reports atomistic simulation based real and complex band structure properties Graphene-Boron nitride heterobilayer and Boron Nitride embedded Graphene nanoribbons which can improve the grapheme and its nanoribbon band structure properties without changing their originality. This part also reports the direct band-to-band tunneling phenomena through the complex band structures and their applications in tunnel field effect transistors(TFETs) which has emerged as a strong candidate for next generation low-stand by power(LSTP) applications due to its sub-60mV/dec Sub threshold slope(SS). As the direct band-to-band tunneling(BTBT) is improbable in Silicon(either its bulk or nanowire form), it is difficult to achieve superior TFET characteristics(i.e., very low SS and high ON cur-rent) from the Silicon TFETs. Whereas, it is explored that much high ON current and very low subthreshold slope in hybrid Graphene based TFET characteristics open a new prospect in future TFETs. The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide materials (MX2)(M=Mo, W;X =S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials(exceptWTe2)in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of thoseMX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthresholdslopeof150 A/mand4 mV/dec, respectively. However, onlytheMoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scalinginsub-10 nm region, new one(1D) and two dimensional(2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. In the first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moore’s law devices also demands the SOI body thickness, TSi0 which is essentially very challenging task in nano-device engineering. To overcome this circumstance, two dimensional crystals in atomically thin layered materials have found great attention for future nanolectronics device applications. Graphene, one layer of Graphite, is such 2D materials which have found potentiality in high speed nanoelectronics applications due to its several unique electronic properties. However, the zero band gap in pure Graphene makes it limited in switching device or transistor applications. Thus, opening and tailoring a band gap has become a highly pursued topic in recent graphene research. The second part of this work reports atomistic simulation based real and complex band structure properties Graphene-Boron nitride heterobilayer and Boron Nitride embedded Graphene nanoribbons which can improve the grapheme and its nanoribbon band structure properties without changing their originality. This part also reports the direct band-to-band tunneling phenomena through the complex band structures and their applications in tunnel field effect transistors(TFETs) which has emerged as a strong candidate for next generation low-stand by power(LSTP) applications due to its sub-60mV/dec Sub threshold slope(SS). As the direct band-to-band tunneling(BTBT) is improbable in Silicon(either its bulk or nanowire form), it is difficult to achieve superior TFET characteristics(i.e., very low SS and high ON cur-rent) from the Silicon TFETs. Whereas, it is explored that much high ON current and very low subthreshold slope in hybrid Graphene based TFET characteristics open a new prospect in future TFETs. The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide materials (MX2)(M=Mo, W;X =S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials(exceptWTe2)in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of thoseMX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthresholdslopeof150 A/mand4 mV/dec, respectively. However, onlytheMoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.