We study and analyze the performance of iterative equalization and decoding (IED) using an M-BCJR equalizer. We use bit error rate (BER), frame error rate simulations and extrinsic information transfer (EXIT) charts to study and compare the performances of M-BCJR and BCJR equalizers on precoded and non-precoded channels. Using EXIT charts, the achievable channel capacities with IED using the BCJR, M-BCJR and MMSE LE equalizers are also compared. We predict the BER performance of IED using the M-BCJR equalizer from EXIT charts and explain the discrepancy between the observed and predicted performances by showing that the extrinsic outputs of the $M$-BCJR algorithm are not true logarithmic-likelihood ratios (LLR's). We show that the true LLR's can be estimated if the conditional distributions of the extrinsic outputs are known and finally we design a practical estimator for computing the true LLR's from the extrinsic outputs of the M-BCJR equalizer.

L'objectif de cette thèse est l'étude de récepteurs MIMO LDPC itératifs. Les techniques MIMO permettent d'augmenter la capacité des réseaux sans fil sans la nécessité de ressources fréquentielles additives. Associées aux schémas de modulations multiporteuses CP-OFDM, les techniques MIMO sont ainsi devenues la pierre angulaire pour les systèmes sans fil à haute efficacité spectrale. La réception optimale peut être obtenue à l'aide d'une réception conjointe (Egalisation/Décodage). Étant très complexe, la réception conjointe n'est pas envisagée et l'égalisation et le décodage sont réalisés disjointement au coût d'une dégradation significative en performances. Entre ces deux solutions, la réception itérative trouve son intérêt pour sa capacité à s'approcher des performances optimales avec une complexité réduite. La conception de récepteurs itératifs pour certaines applications, de type WiFi à titre d'exemple doit respecter la structure du code imposée par la norme. Ces codes ne sont pas optimisés pour des récepteurs itératifs. En observant l'effet du nombre d' itérations dans le processus itératif, on montre par simulation que l'ordonnancement des itérations décodage LDPC/Turbo-égalisation joue un rôle important dans la complexité et le délai du récepteur. Nous proposons de définir des ordonnancements permettant de réduire la complexité globale du récepteur. Deux approches sont proposées, une approche statique ainsi qu'une autre dynamique. Ensuite nous considérons un système multi-utilisateur avec un accès multiple par répartition spatiale. Nous étudions l'intérêt de la réception itérative dans ce contexte tenant en compte la différence de puissance signale utile/interférence.

Crack initiation and propagation in the bladed disks of aero-engines caused by high-cycle fatigue under cyclic loads could result in the breakdown of the engines if not detected at an early stage. Although a number of fault detection methods have been reported in the literature, it still remains very challenging to develop a reliable online technique to accurately diagnose defects in bladed disks. One of the main challenges is to characterize signals contaminated by noises. These noises caused by very dynamic engine operation environment. This work presents a new technique for engine bladed disk crack detection, which utilizes advanced analysis of clearance and time-of-arrival signals acquired from blade tip sensors. This technique involves two stages of signal processing: 1) signal pre-processing for noise elimination from predetermined causes; and 2) signal post-processing for characterizing crack initiation and location. Experimental results from the spin rig test were used to validate technique predictions.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

ABSTRACT SOFT DECODING OF CONVOLUTIONAL PRODUCT CODES ON AN FPGA PLATFORM Sanli, Mustafa M.Sc., Department of Electrical and Electronics Engineering Supervisor: Asst. Prof. Dr. Ali &Ouml / zg&uuml / r YILMAZ September 2005, 79 pages In today&rsquo / s world, high speed and accurate data transmission and storage is necessary in many fields of technology. The noise in the transmission channels and read-write errors occurring in the data storage devices cause data loss or slower data transmission. To solve these problems, the error rate of the received information must be minimized. Error correcting codes are used for detecting and correcting the errors. Turbo coding is an efficient error correction method which is commonly used in various communication systems. In turbo coding, some redundancy is added to the data to be transmitted. The redundant data is used to recover original data from the received data. MAP algorithm is one of the most commonly used soft decision decoding algorithms. In this thesis, hardware implementation of the MAP algorithm is studied. MAP decoding is verified on an FPGA. Virtex2Pro is the platform of choice in this study. The algorithm is written in the VHDL language. A MAP decoder is designed and its operation is verified. Using many MAP decoders concurrently, a convolutional product decoder is implemented as well. Area and speed limitations are discussed.

While the focus of this work is on turbo equalization, there is also an examination of equalization techniques including MMSE linear and DFE equalizers and Precoding. The losses and capacity associated with the ISI channel are also examined. Iterative decoding of concatenated codes is briefly reviewed and the MAP algorithm is explained.

Zugl.: Bremen, Univ., Diss., 2009

Submitted by Eduarda Figueiredo (eduarda.ffigueiredo@ufpe.br) on 2015-03-06T15:14:54Z No. of bitstreams: 2 Tese - Issac.pdf: 1699623 bytes, checksum: 0b927be3b372049f2ce08bca320becfc (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) / Made available in DSpace on 2015-03-06T15:14:54Z (GMT). No. of bitstreams: 2 Tese - Issac.pdf: 1699623 bytes, checksum: 0b927be3b372049f2ce08bca320becfc (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) Previous issue date: 2012-11-22 / FAPEAM / Esta tese apresenta uma medida de complexidade computacional para códigos convolucionais adequada para receptores que implementam o algoritmo de Viterbi em software. A definição desta complexidade envolve a determinação do número de operações aritméticas executadas em um módulo de treliça durante a decodificação, a implementação destas em uma arquitetura de processadores digitais de sinais e a avaliação do respectivo custo computacional de cada operação. Na sequência, esta medida é utilizada para avaliar o impacto do seccionamento do módulo de treliça mínimo. Um conjunto de regras é introduzido para construir padrões de seccionamento que resultem em estruturas de treliça mais compactas e regulares e de mesma complexidade da treliça mínima, constituindo uma alternativa de interesse em aplicações práticas. Finalmente, este trabalho apresenta um método para a construção do módulo de treliça mínimo para codificadores convolucionais sistemáticos recursivos adotados em esquemas turbo. Esta abordagem contribui para a redução da complexidade de decodificação de um decodificador turbo típico operando com codificadores constituintes de taxas altas. Uma busca de códigos é realizada e obtém-se um refinamento da relação complexidade de decodificação versus distância livre efetiva do código turbo.