The Arizona Child Acoustic Database consists of longitudinal audio recordings from a group of children over a critical period of growth and development (ages 2-7 years). The goal of this database is to 1) document acoustic changes in speech production that may be related to physical growth 2) inform development of a model of speech production for child talkers. This work was funded by NSF BSC-1145011 awarded to Kate Bunton, Ph.D. and Brad Story, Ph.D, Principal Investigators. This database contains longitudinal audio recordings of 55 American English speaking children between the ages of 2-7 at 3-month intervals. Since children began the study at different ages, some children have fewer recording sessions than others. The database can also be used to provide cross-sectional data for children of a specific age. Please refer to the subject data table for information on specific sessions available here http://arizona.openrepository.com/arizona/handle/10150/316065. All children were recorded using the same protocol; therefore, task numbers are consistent across children and sessions. A calibration tone is included as Record 1 for all sessions. The speech protocol focused on production of English monopthong and diphthong vowels in isolation, sVd, hVd, and monosyllabic real words. In addition, the protocol includes several nonsense vowel-to-vowel transitions. Speakers were prompted either verbally by investigators or by graphical prompts. Details of the protocol with reference to task numbers can be found in the protocol spreadsheet available here http://arizona.openrepository.com/arizona/handle/10150/316065. Details on data recording: All samples were recorded digitally using an AKG SE 300B microphone with a mouth to mic distance of approximately 10 inches. Signals were recorded digitally using a Marantz PMD671, 16 bit PCM (uncompressed) at 44.1KHz. Recordings are made available in .wav format. Individual zip files contain all recordings from a single session.

M.A. (Psychology) / Please refer to full text to view abstract

Why are dual-task costs reduced with ideomotor (IM) compatible tasks (see e.g. Greenwald & Shulman, 1973)? In a series of experiments, I tested the way in which task structure affects dual-task performance (Halvorson et al., 2012). The results suggest that in some cases, typical dual-task costs arise from task structure rather than response limitations. Further examination of this question has shown that dual-task costs cannot be predicted solely on the basis of the relationship between the stimuli and the responses; the relationship between the tasks, or the task pairing, plays a critical role in whether the tasks overlap and performance is impaired. A series of experiments using novel task pairings showed that when one task uses a spatial central code and the other uses a verbal central code, dual-task costs are eliminated.

Along with the development of VLSI technology and the trend of system-on-chip design, traditional high-level synthesis can not deal with relatively complexity of system-on-chip design. In order to achieve optimal resource allocation, meet its performance and power requirements, and reduce its design time, we need a high-level synthesis software dealing system-level behavior. In consideration of system complexity, we have proposed a high-level synthesis method that synthesis for the task-level grains in a system behavior. This method performs efficient task-level resource allocation, task binding and task scheduling to reach a system design that meets the low performance and power requirements with low implementation cost. We utilize simulated annealing technique to achieve its overall system optimization. We designed and implemented the software design of the task-level high-level synthesis method. In this research, the design consists of three modules: the initial synthesis module, the heuristic movement module and the performance evaluation module. We will use the software to carry out the experiments of the task-level high-level synthesis method on application systems to verify its capability in designing systematic chips.

Thesis (Ph. D.)--University of California, San Diego, 2009. / Title from first page of PDF file (viewed August 20, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 178-184).

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