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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

A pipelined metastability-independent time-to-voltage converter with adjustable resolution /

An, Dong, 1981- January 2007 (has links)
As modern integrated-circuit (IC) technology advances, the level of integration increases, and so too does the clock speed of on-chip signals. As a result, signal integrity has become a major issue on which the circuit performance is largely based. Clock jitter is one of the main issues of signal integrity, and it has become one of the most important circuit limitations. / While extensive research is on-going to reduce clock jitter in ICs, researchers have also been actively involved in discovering ways to characterize it through applications of new time measurement units, or TMUs for short. A number of TMUs have been designed with resolutions down to the picosecond range, among which the time-to-voltage converter (TVC) is a very popular family of circuits used for making highly precise and accurate time measurements. These circuits are popular due to their excellent linearity properties and their ease of fabrication. Nonetheless, these circuits suffer from metastability issues, limiting the lower end of their measurement range. / This thesis first reviews the past TMU circuits, and then presents a TVC architecture that solves the metastability problem. In addition, pipelined operation is added to further increase the throughput of the design. The resolution of the TVC is made adjustable such that it can be used as a stand-alone TMU for different types of applications. The proposed TVC is both verified in simulation and experimentally using a custom designed circuit in a standard 0.18 microm CMOS process supplied by TSMC. Finally, a calibration method is included to further improve the linearity of the overall design.
2

Ada Tools for the Description and Simulation of Digital Signal Processing Systems

Happel, Mark D. 01 January 1987 (has links) (PDF)
While specialized hardware description languages allow for maximum capability and efficiency in a design automation system, the use of a general purpose language in the same role can make the system more available or more available or more practical for a larger set of users. This project demonstrates the use of ADA* for the description and simulation of small digital signal processing systems. Building on conventions and primitives proposed by Denyer and Renshaw, a simple subsystem was described in ADA and then tested with a small simulator also written in ADA. * ADA is a trademark of the United States Department of Defense - ADA Joint Program Office (AJPO).
3

A pipelined metastability-independent time-to-voltage converter with adjustable resolution /

An, Dong January 2007 (has links)
No description available.
4

A Simulation tool for CCS No. 7 network planning and evaluation.

January 1992 (has links)
by Lee Sui Yip. / Thesis (M.Sc.)--Chinese University of Hong Kong, 1992. / Includes bibliographical references. / Chapter Chapter1 --- Introduction / Chapter 1.1 --- Objectives of Common Channel Signalling --- p.1.1 / Chapter 1.1.1 --- Channel Associated Signalling --- p.1-1 / Chapter 1.1.2 --- Common Channel Signalling --- p.1.2 / Chapter 1.2 --- Functional Description --- p.1.3 / Chapter 1.3 --- Signalling Network Basics --- p.1.5 / Chapter 1.4 --- Network Topology --- p.1.9 / Chapter 1.5 --- Signalling Messages --- p.1.13 / Chapter Chapter2 --- Common Channel Signalling No. 7 Network of Hong Kong Telephone / Chapter 2.1 --- System Performance Criteria --- p.2.1 / Chapter 2.1.1 --- Post Dialing Delay --- p.2.2 / Chapter 2.1.2 --- Availability --- p.2.3 / Chapter 2.1.3 --- Survivabiliy --- p.2.3 / Chapter 2.2 --- Implementation Considerations --- p.2.4 / Chapter 2.2.1 --- System Constraints --- p.2.4 / Chapter 2.2.2 --- Number of Signal Transfer Points --- p.2.5 / Chapter 2.2.3 --- Signalling Modes and Assignments --- p.2.6 / Chapter 2.2.4 --- Signalling Link-sets and Diversity --- p.2.7 / Chapter 2.2.5 --- Post Dialing Delay --- p.2.7 / Chapter 2.3 --- The Common Channel Signalling Network of Hong Kong Telephone --- p.2.7 / Chapter Appendix : --- Queuing Delay Estimation --- p.2.9 / Chapter Chapter3 --- Message Routing Policy / Chapter 3.1 --- Originating Signalling Point --- p.3.2 / Chapter 3.2 --- Selection of Signalling Links --- p.3.3 / Chapter 3.3 --- Signal Transfer Points --- p.3.5 / Chapter 3.3.1 --- Same Cluster --- p.3.6 / Chapter 3.3.2 --- Adjacent Clusters --- p.3.6 / Chapter 3.3.3 --- Distant Clusters --- p.3.7 / Chapter 3.4 --- Destination Signalling Point --- p.3.8 / Chapter Appendix : --- STP Stages Estimation --- p.3.9 / Chapter Chapter4 --- Building the Simulation Model / Chapter 4.1 --- Modelling Objective --- p.4.1 / Chapter 4.2 --- The Cluster Level Model --- p.4.2 / Chapter 4.2.1 --- Message Generation --- p.4.2 / Chapter 4.2.2 --- Modelling Message Routing --- p.4.3 / Chapter 4.2.3 --- Modelling Failures --- p.4.5 / Chapter 4.2.4 --- The Simulation Procedures --- p.4.6 / Chapter 4.2.4.1 --- Processes --- p.4.6 / Chapter 4.2.4.2 --- Permanent Entities --- p.4.8 / Chapter 4.2.4.3 --- Initialization Routines --- p.4.9 / Chapter 4.3 --- The Signalling Point Level Model --- p.4.11 / Chapter 4.3.1 --- Message Generation and Routing --- p.4.13 / Chapter 4.3.2 --- Simulation Procedures --- p.4.13 / Chapter Chapter5 --- Network Planning and Evaluation with the Simulation Model / Chapter 5.1 --- Model Testing --- p.5.1 / Chapter 5.2 --- Comparison with Analytical Results --- p.5.2 / Chapter 5.3 --- Modelling with 1 STP Failure --- p.5.5 / Chapter 5.4 --- Simulation with Measured Data --- p.5.8 / Chapter 5.5 --- Network Performance Evaluation --- p.5.15 / Chapter 5.5.1 --- Normal Conditions --- p.5.15 / Chapter 5.5.2 --- STP Failures --- p.5.16 / Chapter 5.5.3 --- Signalling Link-set Failures --- p.5.17 / Chapter 5.6 --- Network Planning --- p.5.19 / Chapter 5.6.1 --- Re-allocation of Signalling Points --- p.5.21 / Chapter 5.6.2 --- Re-configuration of Signalling Network --- p.5.21 / Chapter 5.6.3 --- Associated Link Provision Policy --- p.5.22 / Chapter 5.6.4 --- New Message Routing Policy --- p.5.22 / Discussion and Conclusion / References
5

Réduction de la Consommation Electrique du Contrôle-Commande des Machines Automatisées

Ligeret, Christophe 13 December 2010 (has links) (PDF)
Cette thèse présente une analyse de la consommation d'énergie des systèmes de contrôlecommande électriques des machines automatisées en vue de réduire leur consommation d'énergie. Il est notamment présenté les notions associées aux systèmes de contrôle-commande et il est développé des méthodes et un simulateur de consommation d'énergie destiné à l'analyse de la consommation d'énergie. A partir de ceci, il est réalisé une analyse selon 3 axes : consommation des composants de contrôlecommande pris individuellement, consommation des systèmes de contrôle-commande selon le type de machine et l'assemblage des composants et enfin, consommation dans le temps selon les modes de marche. Ces travaux mettent en évidence que la consommation des systèmes de contrôle-commande est souvent faible comparée à celle des actionneurs, mais qu'il est tout de même possible de réduire d'un facteur 2 la consommation d'énergie.

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