In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width. In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor. Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.