3D stacked ICs (3D-SICs) with multiple dies interconnected by through-silicon-vias(TSVs) are considered as a technology driver and proven to have overwhelming advantagesover traditional ICs with a single die in a package in terms of performance, powerconsumption and silicon overhead. However, these “super chips” bring new challengesto the process of IC manufacturing; among which, testing 3D-SICs is the major andmost complex issue to deal with. In traditional ICs, tests can usually be performedat two stages (test instances), namely: a wafer sort and a package test. Whereas for3D-SICs, tests can be performed after each stacking event where a new die is stackedover a partial stack. This expands the set of available test instances. A combination ofselected test instances where a test is performed (active test instance) is known as a testflow. Test time is a major contributor to the total test cost. Test time changes with theselected test flow. Therefore, choosing a cost effective test flow which will minimizesthe test time is absolutely essential.This thesis focuses on finding an optimal test flow which minimizes the test timefor a given 3D-SIC. A mathematical model has been developed to evaluate the test timeof any test flow. Then a heuristic has been proposed for finding a near optimal test flowwhich minimizes the test time. The performance of this approach in terms of computationtime and efficiency has been compared against the minimum test time obtainedby exhaustive search. The heuristic gives good results compared to exhaustive searchwith much lesser computation time.