Semiconductor supply chain is increasingly getting exposed to Reverse Engineering (RE) of Intellectual Property (IP). Camouflaging of gates in integrated circuits are typically employed to hide the gate functionality to prevent reverse engineering. The functionalities of these gates cannot be found by De-layering as they don’t leave any layout clues. Adversaries perform reverse engineering by replacing the camouflaged gate with the known gate and by developing custom software to determine test patterns. These test patterns are used to analyze the outputs and to conclude the functionality of the camouflaged gate. In this thesis, we show that reverse engineering of camouflaged design can be performed by exploiting the test features of commercial/publicly available Automatic Test Pattern Generation (ATPG) tools. We also propose controllability/observability and Hamming Distance sensitivity based metric to select target gates for camouflaging. Simulations on ISCAS85 benchmarks shows that the proposed techniques can increase the reverse engineering effort significantly by camouflaging small fraction of gates.