No description available.

Thesis (M.S.)--Brigham Young University. Dept. of Chemistry and Biochemistry, 2006. / Includes bibliographical references.

No description available.

Low resistance gate level interconnects can free the design of VLSI circuits from the R-C time constant limitations currently imposed by poly-silicon based technology. The hotwall low pressure chemical vapor deposition of molybdenum and tungsten silicide from their commercially available hexacarbonyls and silane is presented as a deposition method producing IC-compatible gate electrodes of reduced resistivity. Good hotwall deposition uniformity is demonstrated at low temperatures (200 to 300 C). The as-deposited films are amorphous by x-ray diffraction and can be crystallized in subsequent anneal steps with anneal induced film shrinkage of less than 12 percent. Surface oxide formation is possible during this anneal cycle. Auger spectroscopy and Rutherford backscattering results indicate that silicon-rich films can be deposited, and that the concentrations of carbon and oxygen incorporated from the carbonyl source are a function of the deposition parameters. At higher deposition temperatures and larger source throughput the impurity incorporation is markedly reduced. Good film adhesion and excellent step coverage are observed. Electrical measurements show that the film resistivities after anneal are comparable to those of sputtered or evaporated silicide films. Bias-temperature capacitance-voltage measurements demonstrate that direct silicide gate electrodes have properties comparable to standard metal-oxide-silicon systems. The substitution of CVD silicides for standard MOS gate metals appears to be transparent in terms of transistor performance, except for work function effects on the threshold voltage. The large wafer throughput and good step coverage of hotwall low pressure silicide deposition thus promises to become a viable alternative to the poly-silicon technology currently in use.

Advances in microlithography, dry etching, scaling of devices, ion-implantation, process control, and computer aid design brought the integrated circuit technology into the era of VLSI circuits. Those circuits are characterized by high packing density, improved performance, complex circuits, and large chip sizes. Interconnects and their spacing dominate the chip area of VLSI circuits and they degrade the circuit performance through the unacceptable high time delays. Multilayer metallization enables shorter interconnects, ease of design and yet higher packing density for VLSI circuits. It was shown in this dissertation that, tungsten films deposited in a cold-wall LPCVD reactor offer viable solution to the problems of VLSI multilayer interconnects. Experiments showed that LPCVD tungsten films have good uniformity, high purity, low resistivity, low stress-good adherence and are readily patterned into high resolution lines. Moreover, a multilayer interconnect system consisting of three layers of tungsten metallization followed by a fourth layer of aluminum metallization has been designed, fabricated and tested. The interlevel dielectric used to separate the metal layers was CVD phosphorus doped silicon dioxide. Low ohmic contacts were achieved for heavily doped silicon. Also, low resistance tungsten-tungsten intermetallic contacts were obtained. In addition to excellent step coverage, high electromigration resistance of interconnects was realized. Finally, CMOS devices and logic gates were successfully fabricated and tested using tungsten multilayer metallization schemes.

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph. D.)--School of Chemical Engineering, Georgia Institute of Technology, 2004. Directed by Clifford L. Henderson. / Includes bibliographical references (leaves 366-371).

Not available / text

Thesis (M.S.)--Rochester Institute of Technology, 2004. / Typescript. Includes bibliographical references (leaf 100).

No description available.