Important characteristic of any VLSI design circuit is its power reliability, high operating speed and low silicon area implementation. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. The use of pipelines can also provide high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages should also increase and so the memory elements. These memory elements increases the area of implementation and restricts the maximum achievable frequency due to their delays. Memoryless pipelines based on dynamic design address these issues but, still requires high power consumption for the clock signal. In this thesis we present a sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Thus the proposed technique provides advantages over preexisting techniques in terms of power requirement, area over head and operating speed.