This work presents the development of an in-plane vertical micro-coaxial probe using bulk micromachining technique for high frequency material characterization. The coaxial probe was fabricated in a silicon substrate by standard photolithography and a deep reactive ion etching (DRIE) technique. The through-hole structure in the form of a coaxial probe was etched and metalized with a diluted silver paste. A co-planar waveguide configuration was integrated with the design to characterize the probe. The electrical and RF characteristics of the coaxial probe were determined by simulating the probe design in Ansoft’s High Frequency Structure Simulator (HFSS). The reflection coefficient and transducer gain performance of the probe was measured up to 65 GHz using a vector network analyzer (VNA). The probe demonstrated excellent results over a wide frequency band, indicating its ability to integrate with millimeter wave packaging systems as well as characterize unknown materials at high frequencies. The probe was then placed in contact with 3 materials where their unknown permittivities were determined. To accomplish this, the coaxial probe was placed in contact with the material under test and electromagnetic waves were directed to the surface using the VNA, where its reflection coefficient was then determined over a wide frequency band from dc-to -65GHz. Next, the permittivity of each material was deduced from its measured reflection coefficients using a cross ratio invariance coding technique. The permittivity results obtained when measuring the reflection coefficient data were compared to simulated permittivity results and agreed well. These results validate the use of the micro-coaxial probe to characterize the permittivity of unknown materials at high frequencies up to 65GHz.

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Cette thèse est dédiée à l’étude, à la réalisation et à la caractérisation de nouvelles périphéries de TRIAC. L’objet de cette recherche est de réduire l’espace occupé par la périphérie en tentant de conserver le même niveau de performances au blocage. Deux voies d’amélioration ont été poursuivies : l’une concerne la réalisation de caissons d’isolation par thermomigration d’aluminium, l’autre implique l’intégration du silicium poreux dans le caisson d’isolation. La thermomigration d’aluminium est une technique attractive permettant de remplacer les techniques de diffusion conventionnelles. Son industrialisation subit cependant quelques verrous technologiques, notamment le retrait des résidus aluminés et la formation de billes. Deux procédés de gravure ont été développés en vue d’enlever sélectivement l’ensemble de résidus. L’origine des billes a été analysée à l’aide d’observations expérimentales et de modélisations numériques. En utilisant un motif incluant des trous carrés aux intersections, des résultats encourageants ont été démontrés malgré une uniformité thermique encore optimisable. La deuxième voie d’innovation consiste à profiter des propriétés diélectriques du silicium poreux. Un procédé de masquage par fluoropolymère a été développé pour la localisation du silicium poreux. Les conditions d’anodisation adéquates ont été déterminées. La caractérisation de prototypes a montré des tenues au blocage largement améliorées par rapport à l’étude précédente. Bien que les tenues en tension nécessaires n’aient pas été atteintes, des courants de fuite inférieures à 10 μA ont été constatés jusqu’à plusieurs centaines de volts. / This thesis is dedicated to the study, the realization and the testing of “Planar” type TRIAC with novel peripheries. The aim of this research is to shrink the device periphery while maintaining the same level of blocking performances. Two paths of innovation have been pursued: one concerning Al-Si thermomigration for the production of through-wafer isolation walls, and the other involving porous silicon and its integration in the isolation walls. Al-Si thermomigration is an attractive mean allowing to replace conventional diffusion technologies. However, several remaining issues, such as the removal of the unintentional residues and the ball formation phenomenon, block its commercial application. Two different etching procedures have been developed in order to selectively remove all residues. The origin of the ball phenomenon has been analyzed using experimental observations and numerical modeling. By using a new pattern including square holes at intersections, encouraging results have been demonstrated in spite of an optimizable thermal uniformity. The second way of innovation is to take advantage of the dielectric properties of the porous silicon. A fluoropolymer masking process has been developed for local porous silicon formation. The appropriate anodization conditions have been determined. The characterization results showed improved blocking performances compared to the previous study. Although the necessary voltage requirements are not met, leakage currents of less than 10 μA have been observed up to several hundred volts.

The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future high-performance gigascale chip-based systems. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale chips having electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment. A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. In this work, two candidate probe modules were devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The first probe module consists of compliant electrical probes (10^3 probes/cm^2) fabricated alongside grating-in-waveguide optical probes. The second module consists of micro-opto-electro-mechanical-systems (MOEMS)-based microsocket probes (10^4 probes/cm^2) to interface a chip with polymer pillar-based electrical and optical I/Os. High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication are described and numerous possible redistribution schemes are explicated. Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.