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We investigate tiling properties of spectra of measures, i.e., sets Λ in R such that {e 2πiλx : λ ∈ Λ} forms an orthogonal basis in L 2 (µ), where µ is some finite Borel measure on R. Such measures include Lebesgue measure on bounded Borel subsets, finite atomic measures and some fractal Hausdorff measures. We show that various classes of such spectra of measures have translational tiling properties. This lead to some surprizing tiling properties for spectra of fractal measures, the existence of complementing sets and spectra for finite sets with the Coven-Meyerowitz property, the existence of complementing Hadamard pairs in the case of Hadamard pairs of size 2,3,4 or 5. In the context of the Fuglede conjecture, we prove that any spectral set is a tile, if the period of the spectrum is 2,3,4 or 5

<div>Segmented material systems have been shown to provide advantages over monolithic materials including the potential for combinations of properties such as strength, toughness, and ductility that are not otherwise attainable. One such class of segmented system is that of topologically interlocked material (TIM) systems. These are material systems consisting of one or more repeating unit blocks assembled in a planar configuration. When coupled with a bounding frame, this plate-like structure can withstand transverse loads without the use of adhesive or fasteners between blocks.</div><div><br></div><div>One method of generating TIM systems is to start with a 2D tiling and project each edge of the tiles at alternating angles from the tile normal. This work examines 18 unique configurations of TIM systems generated from the Archimedean and the Laves tilings. These systems are constructed as segmented plates having approximately the same number of building blocks and with equivalent overall dimensions so that the effect of the segmentation patterns on the load response of the TIM system can be investigated. Finite element models were utilized to simulate both displacement controlled loading and body force loading of each configuration with various coefficients of friction. The load responses were recorded and the characteristics of chirality and reciprocity of the load response were observed.</div><div><br></div><div>The TIM system configurations in this study resulted in a wide variety of performance. Their range of properties is presented, and a mechanism for strength in a TIM system is postulated. The findings of this work enable the material design space to be expanded by facilitating the creation of material systems with a greater range of properties than is possible with monolithic materials.</div>

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The Kari-Culik tilings are formed from a set of 13 Wang tiles that tile the plane only aperiodically. They are the smallest known set of Wang tiles to do so and are not as well understood as other examples of aperiodic Wang tiles. We show that a certain subset of the Kari-Culik tilings, namely those whose rows can be interpreted as Sturmian sequences (rotation sequences), is minimal with respect to the Z^2 action of translation. We give a characterization of this space as a skew product as well as explicit bounds on the waiting time between occurrences of m × n configurations. / Graduate / 0405

Thesis (Ph.D.)--McMaster University, 2005. / Supervisor: Jean-Pierre Gabardo. Includes bibliographical references (leaves 138-145).

Thesis (Ph. D.)--University of Washington, 1992. / Vita. Includes bibliographical references (leaves [104]-105).

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

The importance of stencil-based algorithms in computational science has focused attention on optimized parallel implementations for multilevel cache-based processors. Temporal blocking schemes leverage the large bandwidth and low latency of caches to accelerate stencil updates and approach theoretical peak performance. A key ingredient is the reduction of data traffic across slow data paths, especially the main memory interface. Most of the established work concentrates on updating separate cache blocks per thread, which works on all types of shared memory systems, regardless of whether there is a shared cache among the cores. This approach is memory-bandwidth limited in several situations, where the cache space for each thread can be too small to provide sufficient in-cache data reuse. We introduce a generalized multi-dimensional intra-tile parallelization scheme for shared-cache multicore processors that results in a significant reduction of cache size requirements and shows a large saving in memory bandwidth usage compared to existing approaches. It also provides data access patterns that allow efficient hardware prefetching. Our parameterized thread groups concept provides a controllable trade-off between concurrency and memory usage, shifting the pressure between the memory interface and the Central Processing Unit (CPU).We also introduce efficient diamond tiling structure for both shared memory cache blocking and distributed memory relaxed-synchronization communication, demonstrated using one-dimensional domain decomposition. We describe the approach and our open-source testbed implementation details (called Girih), present performance results on contemporary Intel processors, and apply advanced performance modeling techniques to reconcile the observed performance with hardware capabilities. Furthermore, we conduct a comparison with the state-of-the-art stencil frameworks PLUTO and Pochoir in shared memory, using corner-case stencil operators. We study the impact of the diamond tile size on computational intensity, cache block size, and energy consumption. The impact of computational intensity on power dissipation on the CPU and in the DRAM is investigated and shows that DRAM power is a decisive factor for energy consumption in the Intel Ivy Bridge processor, which is strongly influenced by the computational intensity. Moreover, we show that highest performance does not necessarily lead to lowest energy even if the clock speed is fixed. We apply our approach to an electromagnetic simulation application for solar cell development, demonstrating several-fold speedup compared to an efficient spatially blocked variant. Finally, we discuss the integration of our approach with other techniques for future High Performance Computing (HPC) systems, which are expected to be more memory bandwidth-starved with a deeper memory hierarchy.

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