<p>FIR (Finite-length Impulse Response) filters are the corner stone of many signalprocessing devices. A lot of research has gone into their development as wellas their effective implementation. With recent research focusing a lot on powerconsumption reduction specially with regards to FPGAs, it was found necessaryto explore FIR filters mapping on FPGAs.</p><p>Time multiplexed FIR filters are also a good candidate for examination withrespect to power consumption and resource utilization, for example when implementedin Field Programmable Gate Arrays (FPGAs). This is motivated by thefact that the usable clock frequency often is higher compared to the required datarate. Current implementations by, e.g., Xilinx FIR Compiler suffer from highpower consumption when the time multiplexing factor is low. Further, it needs tobe investigated how exploiting coefficient symmetry, scaling the coefficients andincreasing the time-multiplexing factor influences the performance.</p>

FIR (Finite-length Impulse Response) filters are the corner stone of many signalprocessing devices. A lot of research has gone into their development as wellas their effective implementation. With recent research focusing a lot on powerconsumption reduction specially with regards to FPGAs, it was found necessaryto explore FIR filters mapping on FPGAs. Time multiplexed FIR filters are also a good candidate for examination withrespect to power consumption and resource utilization, for example when implementedin Field Programmable Gate Arrays (FPGAs). This is motivated by thefact that the usable clock frequency often is higher compared to the required datarate. Current implementations by, e.g., Xilinx FIR Compiler suffer from highpower consumption when the time multiplexing factor is low. Further, it needs tobe investigated how exploiting coefficient symmetry, scaling the coefficients andincreasing the time-multiplexing factor influences the performance.