Tong Ka Yau Dennis. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 77-81). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Progress on the Problem --- p.2 / Chapter 1.3 --- Our Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Background on Retiming --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Preliminaries --- p.7 / Chapter 2.3 --- Retiming Problem --- p.9 / Chapter 3 --- Literature Review on Retiming --- p.10 / Chapter 3.1 --- Introduction --- p.10 / Chapter 3.2 --- The First Retiming Paper --- p.11 / Chapter 3.2.1 --- """Retiming Synchronous Circuitry""" --- p.11 / Chapter 3.3 --- Important Extensions of the Basic Retiming Algorithm --- p.14 / Chapter 3.3.1 --- """A Fresh Look at Retiming via Clock Skew Optimization""" --- p.14 / Chapter 3.3.2 --- """An Improved Algorithm for Minimum-Area Retiming""" --- p.16 / Chapter 3.3.3 --- """Efficient Implementation of Retiming""" --- p.17 / Chapter 3.4 --- Retiming in Physical Design Stages --- p.19 / Chapter 3.4.1 --- """Physical Planning with Retiming""" --- p.19 / Chapter 3.4.2 --- """Simultaneous Circuit Partitioning/Clustering with Re- timing for Performance Optimization" --- p.20 / Chapter 3.4.3 --- """Performance Driven Multi-level and Multiway Parti- tioning with Retiming" --- p.22 / Chapter 3.5 --- Retiming with More Sophisticated Timing Models --- p.23 / Chapter 3.5.1 --- """Retiming with Non-zero Clock Skew, Variable Register, and Interconnect Delay""" --- p.23 / Chapter 3.5.2 --- """Placement Driven Retiming with a Coupled Edge Tim- ing Model""" --- p.24 / Chapter 3.6 --- Post-Retiming Register Placement --- p.26 / Chapter 3.6.1 --- """Layout Driven Retiming Using the Coupled Edge Tim- ing Model""" --- p.26 / Chapter 3.6.2 --- """Integrating Logic Retiming and Register Placement""" --- p.27 / Chapter 4 --- Retiming with Gate and Wire Delay [2] --- p.29 / Chapter 4.1 --- Introduction --- p.29 / Chapter 4.2 --- Problem Formulation --- p.30 / Chapter 4.3 --- Optimal Approach [2] --- p.31 / Chapter 4.3.1 --- Original Mathematical Framework for Retiming --- p.31 / Chapter 4.3.2 --- A Modified Optimal Approach --- p.33 / Chapter 4.4 --- Near-Optimal Fast Approach [2] --- p.37 / Chapter 4.4.1 --- Considering Wire Delay Only --- p.38 / Chapter 4.4.2 --- Considering Both Gate and Wire Delay --- p.42 / Chapter 4.4.3 --- Computational Complexity --- p.43 / Chapter 4.4.4 --- Experimental Results --- p.44 / Chapter 4.5 --- Lin's Optimal Approach [23] --- p.47 / Chapter 4.5.1 --- Theoretical Results --- p.47 / Chapter 4.5.2 --- Algorithm Description --- p.51 / Chapter 4.5.3 --- Computational Complexity --- p.52 / Chapter 4.5.4 --- Experimental Results --- p.52 / Chapter 4.6 --- Summary --- p.54 / Chapter 5 --- Register Insertion in Placement [36] --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Problem Formulation --- p.57 / Chapter 5.3 --- Placement of Registers After Retiming --- p.60 / Chapter 5.3.1 --- Topology Finding --- p.60 / Chapter 5.3.2 --- Register Placement --- p.69 / Chapter 5.4 --- Experimental Results --- p.71 / Chapter 5.5 --- Summary --- p.74 / Chapter 6 --- Conclusion --- p.75 / Bibliography --- p.77