During the last decades, Computer Architecture has experienced a great series of revolutionary changes. The increasing transistor count on a single chip has led to some of the main milestones in the field, from the release of the first Superscalar (1965) to the state-of-the-art Multithreaded Multicore Architectures, like the Intel Core i7 (2009).Moore's Law has continued for almost half of a century and is not expected to stop for at least another decade, and perhaps much longer. Moore observed a trend in the process technology advances. So, the number of transistors that can be placed inexpensively on an integrated circuit has increased exponentially, doubling approximately every two years. Nevertheless, having more available transistors can not be always directly translated into having more performance.The complexity of state-of-the-art software has reached heights unthinkable in prior ages, both in terms of the amount of computation and the complexity involved. If we deeply analyze this complexity in software we would realize that software is comprised of smaller execution processes that, although maintaining certain spatial/temporal locality, imply an inherently heterogeneous behavior. That is, during execution time the hardware executes very different portions of software, with huge differences in terms of behavior and hardware requirements. This heterogeneity in the behaviour of the software is not specific of the latest videogame, but it is inherent to software programming itself, since the very beginning of Algorithmics.In this PhD dissertation we deeply analyze the inherent heterogeneity present in software behavior. We identify the main issues and sources of this heterogeneity, that hamper most of the state-of-the-art processor designs from obtaining their maximum potential. Hence, the heterogeneity in software turns most of the current processors, commonly called general-purpose processors, into overdesigned. That is, they have much more hardware resources than really needed to execute the software running on them. This fact would not represent a main problem if we were not concerned on the additional power consumption involved in software computation.The final goal of this PhD dissertation consists in assigning each portion of software exactly the amount of hardware resources really needed to fully exploit its maximal potential; without consuming more energy than the strictly needed. That is, obtaining complexity-effective executions using the inherent heterogeneity in software behavior as steering indicator. Thus, we start deeply analyzing the heterogenous behaviour of the software run on top of general-purpose processors and then matching it on top of a heterogeneously distributed hardware, which explicitly exploit heterogeneous hardware requirements. Only by being heterogeneity-aware in software, and appropriately matching this software heterogeneity on top of hardware heterogeneity, may we effectively obtain better processor designs.The PhD dissertation is comprised of four main contributions that cover both multithreaded single-core (hdSMT) and multicore (TCA Algorithm, hTCA Framework and MFLUSH) scenarios, deeply explained in their corresponding chapters in the PhD dissertation memory. Overall, these contributions cover a significant range of the Heterogeneity-Aware Processors' design space. Within this design space, we have focused on the state-of-the-art trend in processor design: Multithreaded Multicore (CMP+SMT) Processors.We make special emphasis on the MPsim simulation tool, specifically designed and developed for this PhD dissertation. This tool has already gone beyond this PhD dissertation, becoming a reference tool by an important group of researchers spread over the Computer Architecture Department (DAC) at the Polytechnic University of Catalonia (UPC), the Barcelona Supercomputing Center (BSC) and the University of Las Palmas de Gran Canaria (ULPGC).

Multicore architectures have been one of the primary driving forces in the recent rapid growth in high-end computing systems, contributing to its growing scales and capabilities. With significant enhancements in high-speed networking technologies and protocol stacks which support these high-end systems, a growing need to understand the interaction between them closely is realized. Since these two components have been designed mostly independently, there tend to have often serious and surprising interactions that result in heavy asymmetry in the effective capability of the different cores, thereby degrading the performance for various applications. Similarly, depending on the communication pattern of the application and the layout of processes across nodes, these interactions could potentially introduce network scalability issues, which is also an important concern for system designers. In this thesis, we analyze these asymmetric interactions and propose and design a novel systems level management framework called SIMMer (Systems Interaction Mapping Manager) that automatically monitors these interactions and dynamically manages the mapping of processes on processor cores to transparently maximize application performance. Performance analysis of SIMMer shows that it can improve the communication performance of applications by more than twofold and the overall application performance by 18%. We further analyze the impact of contention in network and processor resources and relate it to the communication pattern of the application. Insights learnt from these analyses can lead to efficient runtime configurations for scientific applications on multicore architectures. / Master of Science

A generalized software capability has been developed for the pin-wise loading optimization of light water reactor (LWR) fuel lattices with the enhanced flexibility of control variables that characterize heterogeneous or blended target pins loaded with non-standard compositions, such as minor actinides (MAs). Furthermore, this study has developed the software coupling to evaluate the performance of optimized lattices outside their reflective boundary conditions and within the realistic three-dimensional core-wide environment of a LWR. The illustration of the methodologies and software tools developed helps provide a deeper understanding of the behavior of optimized lattices within a full core environment. The practical applications include the evaluation of the recycling (destruction) of “undesirable” minor actinides from spent nuclear fuel such as Am-241 in a thermal reactor environment, as well as the timely study of planting Np-237 (blended NpO2 + UO2) targets in the guide tubes of typical commercial pressurized water reactor (PWR) bundles for the production of Pu-238, a highly “desirable” radioisotope used as a heat source in radioisotope thermoelectric generators (RTGs). Both of these applications creatively stretch the potential utility of existing commercial nuclear reactors into areas historically reserved to research or hypothetical next-generation facilities. In an optimization sense, control variables include the loadings and placements of materials; U-235, burnable absorbers, and MAs (Am-241 or Np-237), while the objective functions are either the destruction (minimization) of Am-241 or the production (maximization) of Pu-238. The constraints include the standard reactivity and thermal operational margins of a commercial nuclear reactor. Aspects of the optimization, lattice-to-core coupling, and tools herein developed were tested in a concurrent study (Galloway, 2010) in which heterogeneous lattices developed by this study were coupled to three-dimensional boiling water reactor (BWR) core simulations and showed incineration rates of Am-241 targets of around 90%. This study focused primarily upon PWR demonstrations, whereby a benchmarked reference equilibrium core was used as a test bed for MA-spiked lattices and was shown to satisfy standard PWR reactivity and thermal operational margins while exhibiting consistently high destruction rates of Am-241 and Np to Pu conversion rates of approximately 30% for the production of Pu-238.