A circuit design of baseband transceiver for direct sequence ultra-wide band system is presented in this thesis. A low complexity Viterbi decoder is also proposed. This Viterbi decoder circuit is based on compare-select-add unit and trace-forward architecture. The decision bit operator is reduced to one adder and this can lower down the hardware complexity. Further, two trace-forward operators are used in the survivor management unit. Only two single port SRAM¡¦s with a length of T are applied for reducing the area of memory. The chip is implemented by TSMC standard 0.18-£gm 1P6M CMOS process with core area 1.061 ¡Ñ 1.069 mm2. The post-layout simulation with 1.8V supply at 25 shows that the proposed direct sequence ultra-wide band system of baseband transceiver chip can work above 141 MHz with 86.41 mW power dissipation.