Abstract¡G This thesis mainly implemented an RF transmitter with high efficiency and high linearity. A Cartesian to Polar transformation was implemented by CORDIC algorithm using FPGA. By replacing the envelope detector and limiter in traditional envelope elimination and restoration transmitter, this technique not only achieves more accurate modulation quality, but also becomes more suitable for single chip system. Applying the first order delta-sigma modulation and highly efficient switching-mode DC converter, the envelope signal was amplified highly efficiently. Due to the class-E power amplifier having good linear relation between output voltage and supply voltage, the polar modulation transmitter can achieve high efficiency and high linearity simultaneously. Furthermore, this thesis purposed a new transmitter with two-terminal time-varying modulation. The IQ modulated signal was fed to the input terminal of class-E amplifier, while the envelope signal was used to amplitude modulate the voltage supply terminal. With dynamic input power control, the conversion efficiency and linearity are independent of output power in the purposed architecture. From the experimental results, while transmitting a QPSK-modulated CDMA2000 1x signal with 1.2288 Msps data rate, the transmitter achieve 48 % in drain efficiency, 47 dB in ACPR, and 6 % in EVM at the output power ranging from 10 to 22 dBm.