In this thesis, the low-power design of two popular error-control code decoders has been presented. It first proposes a low-power Viterbi decoder based on the improved reference path generation method which can lead to significant reduction of the memory accesses during the trace-back operation of the survival memory unit. The use of the reference path has been addressed in the past; this mechanism is further extended in this thesis to take into account the selection of starting states for the trace-back and path prediction operations. Our simulation results show that the best saving ratio of memory access can be up to 92% by choosing the state with the minimum state-metric for both trace-back and path prediction. However, the implementation of our look-ahead path prediction initiated from the minimum state will suffer a lot of area overhead especially for Viterbi applications with large state number. Therefore, this thesis instead realizes a 64-state Viterbi decoder whose path prediction starts from the predicted state obtained from the previous prediction phase. Our implementation results show that the actual power reduction ratio ranges from 31% to 47% for various signal-to-noise ratio settings while the area overhead is about 10%. The second major contribution of this thesis is to apply the similar low-power technique to the design of Soft-Output-Viterbi-Algorithm (SOVA) based Turbo code decoders. Our experimental results show that for eight-state SOVA Turbo code, our reference path generation mechanism can reduce more that 95% memory accesses, which can help saving the overall power consumption by 15.6% with a slight area overhead of 3%.

This Diploma thesis deals with Turbo code problems. The Turbo codes belong to the group of error correction codes, sometimes referred to as forward error correcting (FEC) codes or channel codes. This thesis can be thematically divided into two basic parts. The first part describes turbo code encoder and decoder block diagram with the illustration of two most frequently used iterative decoding algorithms (SOVA and MAP). The end of this part contains best known turbo codes, which are used in present communication systems. The second part pursues simulation results for the turbo codes using Binary Phase Shift Keying (BPSK) over Additive White Gaussian Noise (AWGN) channels. These simulations were created in the MATLAB/SIMULINK computer program. It will be shown here, that there exist many different parameters, greatly affecting turbo codes performance. Some of these parameters are: number of decoding iterations used, the input data frame length, generating polynoms and RSC encoders constraint lengths, properly designed interleaving block, decoding algorithm used, etc.