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Availability of historical unit cost data is an important factor in developing accurate project cost estimates. State highway agencies (SHAs) collect data on historical bids and/or production rates, crew sizes and mixes, material costs, and equipment costs, including contractor overhead and profit. The objective of this research is to create a framework to define a standardized and a systematic approach for developing unit costs for construction project estimating. A literature review was conducted that provided an overview of estimating techniques used in project estimating, estimation guidelines maintained by SHAs, and information systems used in the estimation process. After gaining a broad overview of the industry‘s approach to unit cost development, a survey was then conducted. The purpose of the survey was to identify the state of practice in SHAs for unit cost development. The survey helped to identify SHAs doing considerable work in unit cost development and interviews were conducted with these agencies to know their unit cost development process in detail. The results from survey and the interviews were then used in defining the framework. The framework provides a standardized way to use historical data for preparing construction project estimates.

This study investigated the effects of unit price structure, unit price descriptions, and unit price sequence on the demand for money in humans. Six groups of 3 participants solved multiplication problems in exchange for money under various unit prices. Consumption of money decreased as the unit price increased across all conditions. However, the data also showed that: (a) fixed price structures produced slightly more elastic demand than did variable price structures, (b) price descriptions produced more elastic demand under variable price structures but had little or no effect under fixed price structures, and (c) the alternate sequence used with fixed price structures produced slightly more elastic demand.

In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and their advantages and disadvantages. We have mainly focused on current-steering digital-to-analog design for achieving high speed and high performance. The current-steering DAC is designed using binary weighted architecture. The benefits of this architecture is that it occupies less area, consumes less power and the number of control signals required are very less. The requirements for high speed and high performance DAC are discussed in detail. The circuit is implemented in a state-of-the-art 65 nm process, with a supply voltage of 1.2 V and at a sampling speed of 2 GHz. The resolution of the DAC is 8-bits. The design of 8-bit current-steering DAC converts 8 most significant bits (MSBs) into their binary weighted equivalent, which controls 256 unit current sources. The performance of the DAC is measured using the static and dynamic  parameters. In communication applications the static performance measures such as INL and DNL are not of utmost importance. In this work, we have mainly concentrated on the dynamic performance characteristics like SNR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range). For measuring the dynamic parameters, frequency domain analysis is a better choice. Also, we have discussed how the pole-zero analysis can be used to arrive at the dynamic performance metrics of a unit element of the DAC at higher frequencies. Different methods were discussed here to show the effects of poles and zeroes on the output impedance of a unit element at higher frequencies, for example, by hand calculation, using Mathematica and by using cadence. After extensive literature studies, we have implemented a technique in cadence, to increase the output impedance at higher frequencies. This technique is called as “complimentary current solution technique”. This technique will improve the output impedance and SFDR compared to the normal unit element design. Our technique contains mostly analog building blocks, like, current mirrors, biasing scheme and switching scheme and few digital blocks like D-ff (D-flip flop). The whole system is simulated and verified in MATLAB. Dynamic performances of the DAC such as SNR and SFDR are found with the help of MATLAB.