Power efficiency and processor performance demands on modem embedded systems are steadily increasing, and manufacturing improvements are allowing for greater customization of Systems-on-Chip. Meanwhile, the diversification of embedded systems into a growing number of applications, and the continual growth and increasing adoption rate of existing applications drive a trend towards platform based design. Custom and semi-custom platforms allow optimization of hardware to meet the specific needs of individual applications; those specific needs must be determined on a case-by-case basis, but are closely correlated to families of embedded workloads. This thesis presents the embedded system designer with a discussion on available hardware customizations and architectural tradeoffs, categorized in terms of workload and application. Case studies illustrate a process by which the designer can explore such optimizations for their specific application. An in-depth examination is provided for one such tradeoff, on-chip memory configuration, including an empirical analysis of the measurable benefits.

In the last decade, adaptive optics systems have been implemented on all the major ground based telescopes and have proven reliable tools for correcting the image to near the diffraction limit. However, the correction from these systems is limited to a narrow field of view. This dissertation address the challenges of widening the corrected field of single conjugate adaptive optics by properly using statistical information on the optical turbulence profile of the atmosphere above the telescope, and by optimizing the trade-off between image quality and field of view. Altair is the facility adaptive optics system for the 8-meter Gemini North telescope and marks the historical beginning of wide field adaptive optics. Its performance evaluation in Part One is the first on-sky comparison of sparse field images from an altitude-conjugated and a ground-conjugated deformable mirror. All of the other basic aspects of Altair's performance are characterized for use by the Gemini community to plan observations. We also study and report. on techniques for extrapolating the edge of the deformable mirror, a critical step in altitude-conjugated mode. In Part Two we develop a point spread function model for Ground Layer Adaptive Optics (GLAO) that is based on analytic forms of the phase power spectral density. This model has been used for feasibility studies of GLAO on Gemini, and the Thirty Meter Telescope (TMT), currently the most advanced extremely large telescope project. The TMT will be an adaptive telescope that has science goals for the huge 81 square arcminute field of the Wide Field Optical Spectrograph (WFOS). We will show that WFOS-GLAO provides useful gains and will operate in the very wide GLAO (VWGLAO) regime, which has no additional overhead for seeing improved operation. To identify the VWGLAO regime we use statistical turbulence profile models and examine anisoplanatism in terms of image quality metrics relevant to the science that GLAO will likely assist. The VWGLAO regime is where there are useful gains over the theoretical seeing limit for wide field science that measure data collection efficiency as proportional to the product of image quality and the field of view (solid angle). We also show that for many cases VWGLAO will not be impacted by lag anisoplanatism nor by wavefront sensor noise.

A network processor unit (NPU) is a programmable device that consists of several hardware accelerators for wire-speed networking operations. One of the most important functional units in an NPU is packet classification unit (PCU) that classifies data packets based on single or multiple fields of packet header or contents in payload data. Large number of tasks in computer communication require packet classification. Network packet classification requires two types of matching techniques: (i) exact. and (ii) inexact match. There are two solutions for exact match: (i) sequential and (ii) parallel solutions. Inexact match can be of two types: (i) Longest prefix match and (ii) Best match. This dissertation talks about these four techniques required for the PCU. For the sequential solution. we propose a string search algorithm that requires reduced time complexity. It also requires a small amount of memory. arid shows better performance than any other related algorithms as proved by numerical analysis and extensive computer simulations. For parallel solution. we present a systematic technique for expressing the string search algorithm as a regular iterative expression to explore all possible processor arrays. The technique allows some of the algorithm variables to be pipelined while others are broadcast over system-wide buses. Nine possible processor array structures are obtained and analyzed in terms of speed, area. power. and I/O timing requirements. The proposed designs exhibit optimum speed and area complexities. The parallel solution requires an embedding technique that embeds a source processor array onto a target processor array having smaller number of processing elements (PE) to meet the hardware resource constraint. We propose a. novel embed-ding technique. Through numerical analysis and extensive computer simulation. it is proved that the performance of the target array shows the same performance as the source array. For Longest prefix match (LPM), we propose a novel variable-stride multi-bit trie data structure for IP-lookup table to assist. fast IP-lookup and fast lookup table update. In this dissertation. we first explicitly elaborate the solution of a problem in expanding IP (internet protocol) addresses. Through extensive computer simulation on several routing tables. it is proved that our proposed algorithm shows better performance (lookup and update time) than existing algorithms. However. our proposed technique requires larger memory than others. But the memory requirement is quite acceptable considering the current memory availability and price. We propose a novel Best Match technique required to detect best-matched English words of obfuscated spam words. We have used a non-deterministic finite automaton (NFA) to build the English dictionary. We have used dynamic programming with state pruning to detect the best-matched word of an obfuscated spam word in the NFA. We have done extensive numerical simulations to prove the accuracy of our proposed system. Our system can detect best-matched words of the words obfuscated by spammers using five different techniques: insertion, deletion. substitution. trans-pose. and word boundary. Upto our knowledge. no other system can deal with all these obfuscating techniques so quickly as ours.

No description available.

The WTI gene encodes for a transcription factor which is mutated in approximately 15% of sporadic Wilms' tumors (Orkin et al., 1984; Fearon et al., 1990). Mutations in WTI are also associated with a number of clinical disorders such as Denys-Drash and Frasier syndromes. which are distinguished by genitourinary malformation and kidney disease (McTaggart et al., 2001). The nucleic acid binding domain of WTI is comprised of four tandemly arranged C2H2 type zinc fingers (Haber et al., 1990; Rauscher et al.. 1990; Morris et al., 1991). The WT1 transcript is regulated by two different alternative splicing events. The first alternative splice introduces 17 amino acids between the proline-rich amino terminus and the zinc finger domain (Haber et al.. 1991). The second alternative splice inserts the amino acids KTS between zinc fingers 3 and 4 (Haber et al., 1991). The +KTS and -KTS isoforms of WT1 have different nucleic acid binding specificities. The .-KTS isoform readily binds to specific sequences in both DNA and RNA. while the +KTS isoform only binds to specific sequences in RNA (Zhai et al., 2001). The RNA binding capabilities of the +KTS variant combined with its presence in spliceosomes (Davies et al.. 1998) and nuclear poly(A)+ ribonucleoprotein (Ladomery et at., 1999), suggests that it is involved in RNA metabolism. WT1 has been shown to interact with RNA through the zinc finger domain (Caricasole et al, 1996), but as of yet. there is not a purified crystal structure of WT l interacting with RNA. There have been many experiments that have attempted to decipher the mechanism for WTI RNA binding (Caricasole et al, 1996; Bardeesy and Pelletier, 1998). One zinc finger knock-out experiment has proposed that it is zinc finger number 1 which plays the most important role in this RNA interaction (Caricasole et at, 1996) while another suggests that it is finger 4 (Bardeesy and Pelletier, 1998). In order to determine which zinc finger of WT 1 is the most crucial for RNA binding, WT 1 swap mutants and deletion mutants were created by PCR and a filter binding assay was employed to determine dissociation binding constants of the mutant proteins with the WT1-specific RNA aptamer Pe122. The mutant W12P8W4, which has finger 3 of WTI replaced with finger 8 of the zinc finger protein p43, demonstrated a relative affinity for Pe122 of less than 0.29. The deletion mutant WTlAF4 which had finger 4 of WTI deleted showed no affinity for Pe122 RNA, while the mutant Wp4 which had finger 4 of WTI replaced with finger 9 of p43 demonstrated a 10 times greater affinity for Pe122 than wild type WT1. These results suggest that finger 3 makes important residue-base contacts with the RNA and that perhaps finger 4 confers some sort of stability to the WT1-RNA complex.

Can one classify biochemical pathways based on their topology? What is the topology of a biochemical pathway? What are the fundamental principles underlying different biochemical pathways involved in similar functional areas? Will one be able to characterize pathway "motifs" similar to motifs in proteins - i.e. reoccurring patterns in pathways? This thesis describes an attempt to develop a quantitative framework for the general representation and comparison of biochemical pathways. This quantitative framework involves a mathematical model to represent biochemical pathways and a set of similarity criteria to compare these biochemical pathways. We anticipate that such a tool would allow biologists to answer important questions such as the ones mentioned above.

In order to elucidate the molecular and biochemical events occurring in embryogenesis in Douglas-fir (Pseudotsuga menziesii [Mirb.] Franco), an essential gene expressed highly during early embryogenesis was identified, cloned and further characterized in this study. Douglas-fir LYR/LVR eDNA was obtained using RT-PCR with specific primers. followed by cloning and sequencing. Northern blot analysis showed higher amounts of LYR/LVR transcripts in early-cotyledonary embryonic stages and megagametophytes when compared with mid- and late-cotyledonary embryos. LYR/LVR transcript levels declined in seeds (mature embryos) and seedlings. Differential regulation of LYR/LVR gene expression with response to brassinosteroid treatment of Douglas-fir seeds was studied. LYR/LVR mRNA showed higher accumulation in seeds treated with different concentrations of brassinosteroids. Bioinformatic analysis showed that Douglas-fir LYR/LVR protein may be an essential inner mitochondrial protein, NADH oxidoreductase necessary for energy production. The phylogenetic tree analysis was used to investigate the evolutionary relationship of the newly identified Douglas-fir LYR/LVR protein with closely related proteins (LYR family) in different organisms. InterPro, UniProt and Pfam results showed the sequence similarity of Douglas-fir LYR/LVR protein with other related members in Arabidopsis thaliana and Oryza sativa, indicating that the LYR complex contains short stretches of closely related proteins that are essential for energy production. Amino acids 19-90 in the LYR/LVR protein were highly conserved and is likely the functional LYR motif necessary for oxidoreductase activity.

Theileria parva is an intracellular protozoan parasite and the causative agent of the lethal livestock disease East Coast fever (ECF). Research has shown that a protective cell-mediated immune response against parasite-infected lymphocytes is capable of clearing the host of T. parva (Pearson et al. 1979), leaving the host solidly immune to reinfection. The work presented in this thesis describes my attempts to develop a method for identification of major histocompatibility complex class I-associated T. parva peptides involved in eliciting this protective cell-mediated immune response. The soluble chaperone gp96 interacts with peptides destined for association with major histocompatibily complex class I molecules and is therefore a source of T. parva peptides that interact with extracellular immune effectors. Using sensitive mass spectrometry methods the gp96-chaperoned peptide proteome from model parasite infected T lymphocytes was compared to an uninfected T cell line. With our findings we have demonstrated proof of concept for a highly sensitive method for the elucidation of potentially immunogenic peptides capable of initiating a protective immune response against the intracellular parasite T parva.

Cationic Antimicrobial Peptides (CAPs) exhibit broad-spectrum activity against a variety of microbial pathogens at concentrations that are non-toxic to higher eukaryotes. These properties make them excellent candidates for both pharmaceutical and agricultural applications. Here BMAP18, a CAP with an especially high charge to mass ratio, is evaluated for efficient production of the peptide and enhancement of disease resistance in transgenic potato. In vitro analyses indicated that BMAP18 had potent activity against a variety of clinically and agriculturally relevant pathogens, including the protozoan parasite Trypanosoma brucei. In planta activity was assessed by transformation of potato (Solanum tuberosum L.) plants with a synthetic BMAP18 gene under control of the enhanced CaMV 35S promoter or the Douglas-fir lumina] Binding Protein (PmBiP) promoter. Stable transformants expressing the transgene were shown to accumulate the peptide and exhibited enhanced resistance to Fusarium wilt and bacterial soft rot caused by Erwinia caratovora.

In this dissertation, four approaches to improve Voice over Internet Protocol (VoIP) security is proposed. The first two approaches are aimed at encrypting/decrypting and authenticating VoIP packets, whereas the last two approaches are aimed at key exchange and user authentication. For the first contribution, a reconfigurable, high throughput hardware implementation for the different block cipher operational modes is proposed. The proposed architecture is unified: and it combines multiple related functions on the same architecture. In other words, it has the ability to encrypt/decrypt a plaintext/ciphertext efficiently using different operational modes. Moreover, it has the ability to ensure data integrity using different operational modes. The proposed architecture is tested using the most widely used block ciphers: DES, TDES, AES-128 AES-192, AES-256, and IDEA. The proposed architecture implementation i, ;anal z d and evaluated in comparing it against other iniplenientaticls. Eta, the second contribution, a high speed, deep-pipelined architecture for AES algorithm based on the composite field approach targeting VoIP applications is proposed. A new algorithm for finding the isomorphic mapping matrix to work for any irreducible polynomial, not only the primitive polynomials, is proposed. Moreover, the modified algorithm is used to find the optimum matrix that gives the minimum delay. The matrix is then used to implement the SubBytes/InvSubBytes transformation using composite fields, which in turn allows Its to design a very high speed deep-pipelined architecture. As a result of using the optimized matrix, a processing throughput of 49.401 Gbps is achieved, which is twice as fast as the fastest design introduced before. Another feature of this architecture is the separation of the encryption circuit from the decryption circuit to allow concurrent encryption and decryption, which facilitates full duplex encryption/decryption for VolP applications. For the third contribution. a high speed. low area ALU to perform field operations required for cryptographic applications is proposed. Although the proposed architecture- works for any cryptographic application, an ECC implementation for VoIP applications is targeted. A processor array design space exploration for GF(2m) multiplier is conducted, fins exploration results in different processor array configurations. Among these configurations, the fastest one is chosen since VolP applications are targeted. The multiplier architecture is then modified to work as a squarer. Based on the multiplier architecture, a unified architecture to calculate addition, multiplication, squaring, and inversion is proposed. The overall area is optimized by using three type's ''1 processing elements instead NI using a . e!;'tdeir processing element everywhere. NIST-recommended irreducible polynomials is used. which makes our deign secure and more suitable for cryptographic applications. The proposed architecture is implemented for GF(2 163). GF(2 283) and GF(2 571) on a Xilinx XC2V 4000-6 device to verify the proposed architecture and measure its performance. A maximum frequency of 261 MHz is achieved- which allows the architecture to calculate GE(2 163) multiplication in 640 ns and inversion in 1-40.357. As a fourth contribution. a high speed ECC architecture based on a high-radix scalar multiplication is proposed. This architecture is optimized for VoIP applications First. a new high-radix scalar multiplication algorithm is proposed. Then. a merged double-and-add elliptic curve ALU based on the proposed algorithm is designed. The merged double-and-add ALU combines point doubling and adding operations on one architecture. which in turn reduces the critic-al path delay. The ECC' processor utilizes the previously proposed field ALU. which implements Addition. squaring. multiplication. and division over GF(2m) A maximum frequency of 253 MHz is achieved. which allows the architecture to calculate GF(2 163) scalar multiplication for radix 2 8 in 9 u.s. At a minimum our results for GF(2 163). show a speedup ranging from 1.5 to 326 times in comparison to previous FPGA implementations and a speedup ranging from 1.1 to .5.6 times in comparison to previous ASPIC implementations.