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Energy-Efficient Devices and Circuits for Ultra-Low Power VLSI ApplicationsLi, Ren 04 1900 (has links)
Nowadays, integrated circuits (IC) are mostly implemented using Complementary Metal Oxide Semiconductor (CMOS) transistor technology. This technology has allowed the chip industry to shrink transistors and thus increase the device density, circuit complexity, operation speed, and computation power of the ICs. However, in recent years, the scaling of transistor has faced multiple roadblocks, which will eventually lead the scaling to an end as it approaches physical and economic limits. The dominance of sub-threshold leakage, which slows down the scaling of threshold voltage VTH and the supply voltage VDD, has resulted in high power density on chips. Furthermore, even widely popular solutions such as parallel and multi-core computing have not been able to fully address that problem. These drawbacks have overshadowed the benefits of transistor scaling. With the dawn of Internet of Things (IoT) era, the chip industry needs adjustments towards ultra-low-power circuits and systems. In this thesis, energy-efficient Micro-/Nano-electromechanical (M/NEM) relays are introduced, their non-leaking property and abrupt switch ON/OFF characteristics are studied, and designs and applications in the implementation of ultra-low-power integrated circuits and systems are explored. The proposed designs compose of core building blocks for any functional microprocessor, for instance, fundamental logic gates; arithmetic adder circuits; sequential latch and flip-flop circuits; input/output (I/O) interface data converters, including an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC); system-level power management DC-DC converters and energy management power gating scheme. Another contribution of this thesis is the study of device non-ideality and variations in terms of functionality of circuits. We have thoroughly investigated energy-efficient approximate computing with non-ideal transistors and relays for the next generation of ultra-low-power VLSI systems.
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A superconducting software defined radio frontend with application to the Square Kilometre ArrayVolkmann, Mark Hans 12 1900 (has links)
Thesis (PhD)-- Stellenbosch University, 2013. / ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a
better instrument. The largest radio telescope in the world will consist of
several arrays, the largest of which, consisting of more than 3000 dishes, will
be situated primarily in South Africa. The ambitions of the SKA are grand
and their realisation requires technology that does not exist today.
Current plans see signals in the band of interest ampli ed, channelised,
mixed down and then digitised. An all-digital frontend could simplify receiver
structure and improve its performance. Semiconductor (analog-to-digital converters)
ADCs continue to make great progress and will likely nd applications
in the SKA, but superconductor ADCs bene t from higher clock speeds
and quantum accurate quantisation. We propose a superconducting softwarede
ned radio frontend.
The key component of such a frontend is a superconducting
ash ADC.
We show that employing such an ADC, even a small- to moderately-sized one,
will signi cantly improve the instantaneous bandwidth observable by the SKA,
yet retain adequate signal-to-noise ratio so as to achieve a net improvement
in sensitivity. This improvement could approach factor 2 when compared to
conventional technologies (at least for continuum observations). We analyse
key components of such an ADC analytically, numerically and experimentally
and conclude that fabrication of such an ADC for SKA purposes is certainly
possible and useful.
Simultaneously, we address the power requirements of high-performance
computing (HPC). HPC on a hitherto unprecedented scale is a necessity for
processing the vast raw data output of the SKA. Utilising the ultra-low-energy
switching events of superconducting switches (certain Josephson junctions),
we develop rst demonstrators of the promising eSFQ logic family, achieving
experimentally veri ed shift-registers and deserialisers with sub-aJ/bit energy requirements. We also propose and show by simulation how to expand the
applicability of the eSFQ design concept to arbitrary (unclocked) gates. / AFRIKAANSE OPSOMMING: Supergeleier-elektronika kan 'n beter instrument maak van die \Square Kilometre
Array" (SKA). Die wêreld se grootse radioteleskoop sal bestaan uit etlike
skikkings, waarvan die grootste - met meer as 3 000 skottels - hoofsaaklik
in Suid-Afrika gesetel sal wees. Die SKA is ambisieus en vereis tegnologie wat
nog nie vandag bestaan nie.
Volgens huidige planne sal seine in die band van belang versterk, gekanalisieer,
afgemeng en dan versyfer word. 'n Heel-digitale kopstuk sal die ontvangerstruktuur
kan vereenvoudig en sy prestasie kan verbeter. Halfgeleier
analoog-na-digital omsetters (ADOs) verbeter voortdurend en sal waarskynlik
toepassings in die SKA vind, maar supergeleier ADOs trek voordeel uit
hoër klok spoed en kwantumakkurate kwantisering. Ons stel 'n supergeleier
sagteware-gede nieerde radio kopstuk voor.
Die sleutelkomponent van so 'n kopstuk is 'n supergeleier \
ash" ADO.
Ons toon hoe die gebruik van so 'n ADO, selfs een van klein tot matige bisgrootte,
die oombliklike bandwydte waarneembaar deur die SKA aansienlik sal
verbeter en 'n voldoende sein-tot-ruis verhouding sal behou, en gevolglik 'n
netto verbetering in sensitiwiteit sal bereik. Hierdie verbetering kan, vergeleke
met konvensionele tegnologie, 'n faktor van 2 nader (ten minste vir kontinuum
waarnemings). Ons analiseer belangrike komponente van so 'n ADO analities,
numeries and eksperimenteel en lei af dat die vervaardiging van so 'n ADO vir
SKA doeleindes beide moontlik en nuttig is.
Terselfdertyd spreek ons die drywingsverkwisting van Hoë-verrigting rekenaars
aan. Sulke rekenaars van 'n tot dusver ongekende skaal is 'n noodsaaklikheid
vir die verwerking van die enorme rou data uitset van die SKA. Deur
die gebruik van die ultra-lae-energie skakels van supergeleier skakelaars (sekere Josephson-vlakke), ontwikkel ons die eerste demonstratiewe hekke van die veelbelowende
eSFQ logiese familie, en toon eksperimenteel bevestigte skuifregisters
en deserieëliseerders met sub-aJ/bis energievereistes. Ons stel verder voor
en wys met simulasies hoe om die toepaslikheid van die eSFQ ontwerpkonsep
na arbitr^ere (ongeklokte) hekke uit te brei.
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