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A Systolic Array Based Reed-Solomon Decoder Realised Using Programmable Logic DevicesBiju, S., Narayana, T. V., Anguswamy, P., Singh, U. S. 11 1900 (has links)
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / This paper describes the development of a Reed-Solomon (RS) Encoder-Decoder which implements the RS segment of the telemetry channel coding scheme recommended by the Consultative Committee on Space Data Systems (CCSDS)[1]. The Euclidean algorithm has been chosen for the decoder implementation, the hardware realization taking a systolic array approach. The fully pipelined decoder runs on a single clock and the operating speed is limited only by the Galois Field (GF) multiplier's delay. The circuit has been synthesised from VHDL descriptions and the hardware is being realised using programmable logic chips. This circuit was simulated for functional operation and found to perform correction of error patterns exactly as predicted by theory.
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