Η μεταπτυχιακή αυτή εργασία μπορεί να χωριστεί σε δύο λογικά μέρη (Μέρος Α’ και Μέρος Β’). Το πρώτο μέρος αφορά τον έλεγχο ορθής λειτουργίας ψηφιακών κυκλωμάτων χρησιμοποιώντας το μοντέλο των Μεταβατικών (Transient) σφαλμάτων και πιο συγκεκριμένα περιλαμβάνει την μελέτη για το μοντέλο, τρόπο λειτουργίας και την υλοποίηση ενός Εξομοιωτή Μεταβατικών Σφαλμάτων (Transition Faults Simulator). Ο εξομοιωτής σφαλμάτων αποτελεί το πιο σημαντικό μέρος της αλυσίδας εργαλείων που απαιτούνται για τον σχεδιασμό και εφαρμογή τεχνικών ελέγχου ορθής λειτουργίας και η ύπαρξη ενός τέτοιου εργαλείου επιτρέπει την μελέτη νέων τεχνικών ελέγχου κάνοντας χρήση του Μεταβατικού μοντέλου σφαλμάτων. Το δεύτερο μέρος της εργασίας συνοψίζει την μελέτη που πραγματοποιήθηκε για την δημιουργία ενός νέου αλγόριθμου επιλογής διανυσμάτων ελέγχου στην περίπτωση των Test Set Embedding τεχνικών ελέγχου. Ο αλγόριθμος επιτυγχάνει σημαντικές μειώσεις τόσο στον όγκο των απαιτούμενων δεδομένων που είναι απαραίτητο να αποθηκευτούν για την αναπαραγωγή του ελέγχου, σε σχέση με τις κλασικές προσεγγίσεις ελέγχου, όσο και στο μήκος των απαιτούμενων ακολουθιών ελέγχου που εφαρμόζονται στο υπό-έλεγχο κύκλωμα σε σχέση με προγενέστερους Test Set Embedding αλγορίθμους. Στο τέλος του μέρους Β’ προτείνεται μία αρχιτεκτονική για την υλοποίηση του αλγόριθμου σε Built-In Self-Test περιβάλλον ελέγχου ορθής λειτουργίας ακολουθούμενη από την εκτίμηση της απόδοσης αυτής και σύγκριση της με την καλύτερη ως τώρα προτεινόμενη αρχιτεκτονική που υπάρχει στην βιβλιογραφία (Βλέπε Παράρτημα Α). / The thesis consists of two basic parts that apply in the field of VLSI testing of integrated circuits. The first one concludes the work that has been done in the field of VLSI testing using the Transient Fault model and more specifically, analyzes the model and the implementation of a Transition Fault Simulator. The transient fault model moves beyond the scope of the simple stuck-at fault model that is mainly used in the literature, by introducing the concept of time and therefore enables the testing techniques to be more precise and closer to reality. Furthermore, a fault simulator is probably the most important part of the tool chain that is required for the design, implementation and study of vlsi testing techniques and therefore having such a tool available, enables the study of new testing techniques using the transient fault model. The second part of the thesis summaries the study that took place for a new technique that reduces the test sequences of reseeding-based schemes in the case of Test Set Embedding testing techniques. The proposed algorithm features significant reductions in both the volumes of test data that are required to be stored for the precise regeneration of the test sequences, and the length of test vector sequences that are applied on the circuit under test, in comparison to the classical proposed test techniques that are available in the literature. In addition to the algorithm, a low hardware overhead architecture for implementing the algorithm in Built-in Self-Test environment is presented for which the imposed hardware overhead is confined to just one extra bit per seed, plus one, very small, extra counter in the scheme’s control logic. In the end of the second part, the proposed architecture is compared with the best so far proposed architecture available in the literature (see Appendix A)

Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the transistor count is as large as billions of gate for some of the microprocessors. The design complexity is further projected to increase in the coming years in accordance with Moore's law. The larger gate count and integration of multiple functionalities are the causes for higher test power dissipation, test time and data volume. The dynamic power dissipation during scan testing, i.e. during scan shift, launch and response capture, are major concerns for reliable as well as cost effective testing. Excessive average power dissipation leads to a thermal problem which causes burn-out of the chip during testing. Peak power on other hand causes test failure due to power induced additional delay. The test failure has direct impact on yield. The test power problem in modern 3D stacked based IC is even a more serious issue. Estimating the worst case functional power dissipation is yet another great challenge. The worst case functional power estimation is necessary because it gives an upper bound on the functional power dissipation which can further be used to determine the safe power zone for the test. Several solutions in the past have been proposed to address these issues. In this thesis we have three major contributions: 1) Sequential scan chain reordering, and 2) JScan-an alternative Joint-scan DFT architecture to address primarily the test power issues along with test time and data volume, and 3) an integer linear programming methodology to address the power estimation problem. In order to reduce test power during shift, we have proposed a graph theoretic formulation for scan chain reordering and for optimum scan shift operation. For each formulation a set of algorithms is proposed. The experimental results on ISCAS-89 benchmark circuit show a reduction of around 25% and 15% in peak power and scan shift time respectively. In order to have a holistic DFT architecture which could solve test power, test time, and data volume problems, a new DFT architecture called Joint-scan (JScan) have been developed. In JScan we have integrated the serial and random access scan architectures in a systematic way by which the JScan could harness the respective advantages from each of the architectures. The serial scan architecture from test power, test time, and data volume problems. However, the serial scan is simple in terms of its functionality and is cost effective in terms of DFT circuitry. Whereas, the random ac-cess scan architecture is opposite to this; it is power efficient and it takes lesser time and data volume compared to serial scan. However, the random access scan occupies larger DFT area and introduces routing congestion. Therefore, we have proposed a methodology to realize the JScan architecture as an efficient alternative for standard serial and random access scan. Further, the JScan architecture is optimized and it resulted into a 2-Mode 2M-Jscan Joint-scan architecture. The proposed architectures are experimentally verified on larger benchmark circuits and compared with existing state of the art DFT architectures. The results show a reduction of 50% to 80% in test power and 30% to 50% in test time and data volume. The proposed architectures are also evaluated for routing area minimization and we obtained a saving of around 7% to 15% of chip area. Estimating the worst case functional power being a challenging problem, we have proposed a binary integer linear programming (BILP) based methodology. Two different formulations have been proposed considering the different delay models namely zero-delay and unit-delay. The proposed methodology generates a pair or input vectors which could toggle the circuit to dissipate worst power. The BILP problems are solved using CPLEX solver for ISCAS-85 combinational benchmark circuits. For some of the circuits, the proposed methodology provided the worst possible power dissipation i.e. 80 to 100% toggling in nets.