According to references, testing and verification of a hardware circuit project occupy about 60%˜70% of project time. Now that product cycle time is decreasing, verification methodology is an important parameter for effective and successful completion of a design project. Enhanced processor functions also make verification conditions more difficult. In this thesis the processor SYS32IME III, which is constructed based on architecture of ARM 1022E, is verified by using V5TE instruction set. This thesis focus on processor verification flow and others to help verification method. The verification language that is used to help generate testbench are described in this paper. Also, corner cases are generated, producing test cases that may be reused in different verification environments. Lastly, errors from CPU architecture, verification environments, interface wrapper and instruction set simulator were found in different verification environment and fixed. To conclude the study, insertion of self-implemented RTL monitor circuit into CPU architecture supply verification information about testbench¡¦s coverage of functional verification.

This Master’s thesis deals with digital decimation filter design for undersampling and filtering of sigma-delta ADC signal. Filter cascade is designed in Matlab according to given requirements and is then described in VHDL language aiming for minimum area. Implemented filter functionality is compared to Matlab-generated reference filters in created verification environment. Finally the design is synthesized in specified technology and verified on gate level.

Made available in DSpace on 2014-12-17T14:55:40Z (GMT). No. of bitstreams: 1 AdautoLT.pdf: 2061017 bytes, checksum: 12a139ba25174e3b22d08cf31c934500 (MD5) Previous issue date: 2009-09-04 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / This work proposes a new methodology to verify those analog circuits, providing an automated tools to help the verifiers to have a more truthful result. This work presents the development of new methodology for analog circuits verification. The main goal is to provide a more automated verification process to certify analog circuits functional behavior. The proposed methodology is based on the golden model technique. A verification environment based on this methodology was built and results of a study case based on the validation of an operational amplifier design are offered as a confirmation of its effectiveness. The results had shown that the verification process was more truthful because of the automation provided by the tool developed / O presente trabalho tem como objetivo desenvolver uma ferramenta de verifica??o para circuitos anal?gicos. O principal objetivo desta ? aumentar a automa??o dos processos de verifica??o. Al?m disso, proporcionar a constru??o de um ambiente de verifica??o capaz de gerar relat?rios ao longo deste processo. Esta metodologia ? baseada na t?cnica do Modelo de Ouro, no entanto, ela tamb?m prop?e uma segunda t?cnica para verificar o modelo de refer?ncia, para se obter resultados mais confi?veis. A metodologia foi utilizada, como estudo de caso, na verifica??o de um amplificador operacional