In order to correctly perform circuit simulation, it is crucial that parasitic capacitances near devices are accurately extracted and are consistent with the SPICE models. Although 3D device simulation can be used to extract such parasitics, it is expensive and does not consider the effects of nearby interconnect and devices in a layout. Conventional rule-based layout parasitic extraction (LPE) tools which are used for interconnect extraction are inaccurate in modeling 3D effects near devices. In this thesis, we propose a methodology which combines 3D field solver based extraction with the ability to exclude specific parasitics from among the parameters in the SPICE model. We use this methodology to extract parasitics due to fringing fields and sidewall capacitances in MOSFETs, bipolar transistors and FinFETs in advanced process nodes. We analyze the importance of considering layout and process variables in device extraction by comparing with standard SPICE models. The results are validated by circuit simulation using predictive technology models and test chips. We also demonstrate the versatility of this flow by modeling the capacitance contributions of the raised gate profile in nanoscale FinFETs.

This research thesis seeks to investigate a new method to sense the classical Hall effect in Hall devices under the influence of a magnetic field primarily manufactured in complementary metal oxide semiconductor (CMOS) technologies. The thesis poses a research question enabling the investigation into whether or not the geometrical factor in a classical Hall device can be improved by proposing a new method to sense the Hall effect indirectly in standard CMOS technology. State of the art Hall effect devices rely on low ohmic contacts to sense the Hall voltage effect. These contacts along with the geometry can have an adverse effect on the Hall device sensitivity. Furthermore, the Hall voltage in Silicon can be very limited in comparison to high mobility semiconductor materials. It was found that by replacing the highly doped n-type sensing contacts of the Hall device with highly doped p-type contacts, a vertical bipolar junction transistor could be formed. This transistor, normally considered a parasitic element, ultimately leads to a very useful sensing technique in which the Hall current is sensed and amplified by the transistor forward gain, β + 1. The Hall effect appears as a current through the emitter of the transistor. The major contribution of this research resides in a novel method to measure as well as amplify the Hall effect in a square n-well plate manufactured on a standard CMOS technology. The research also bridges the gap found in literature on the subject of direct versus indirect Hall sensing techniques. The outcome of the research also addresses practical implementations of such alternate methods as well as the effect the methods have on fundamental noise limits and differences in noise between the proposed method and traditional methods. The device although not improving the fundamental geometrical factor of the plate which was found to be dominated by the geometry itself, was proven to be functional as well as behaving according to Hall effect theory. Furthermore, the gain that even low forward gain bipolar transistors contribute to the signal, more than compensates for the loss of Hall effect contributed by the geometrical correction factor. The method also contributes less noise in comparison to typical traditional methods of Hall voltage amplification using operational amplifiers. The proposed method thus allows for a very simple measuring technique that is compatible with standard CMOS technology processes. ## Hierdie navorsings tesis is gemik daarop om 'n nuwe meetmetode te ondersoek om die klassieke Hall effek te meet in Hall toestelle onder die invloed van 'n magneetveld wat primér in komplementêre metaaloksied-halfgeleiertegnologie (CMOS) vervaardig word. Die tesis stel 'n navorsingsvraag wat lei tot die ondersoek van die vraag of die geometriese faktor in 'n klassieke Hall toestel verbeter kan word deur om 'n nuwe metode voor te stel om die Hall effek indirek te meet in standaard CMOS tegnologie. Nuutste navorsing oor meetmetodes in Hall effek toestelle, maak nog steeds staat op lae ohmiese kontakte om die Hall spanning effek te meet. Hierdie kontakte saam met die meetkunde van die toestel, het 'n nadelige uitwerking op die Hall toestel se sensitiwiteit. Verder is die Hall spanning in Silikon baie beperk met vergelyking tot hoë mobiliteit halfgeleier materiale. Daar is gevind dat deur die vervanging van die hoogs gedoteerde n-tipe meetkontakte van die Hall toestel met hoogs gedoteerde p-tipe kontakte, kan vertikale bipolêre transistors gevorm word. Hierdie transistor, gewoonlik beskou as 'n parasitiese element, lei tot 'n baie nuttige meet tegniek waarin die Hall stroom gemeet en versterk word deur die transistor se voorwaartse wins, β + 1. Die Hall effek verskyn as 'n stroom deur die emittor van die transistor. Die grootste bydrae van hierdie navorsing lê in 'n nuwe metode om die Hall effek in 'n vierkantige n-dam plaat wat in standaard CMOS tegnologie vervaardig is te meet sowel as om die sein te versterk. Die navorsing oorbrug ook die gaping gevind in literatuur oor die onderwerp van direkte teenoor indirekte Hall meet tegnieke. Die uitkoms van die navorsing spreek ook die praktiese implementering van die meetmetode aan sowel as die effek wat die meetmetode op fundamentele ruisgrense en verskille in ruis tussen die voorgestelde meetmetode en tradisionele meetmetodes het. Die toestel, hoewel nie gelei het tot ‘n verbetering van die fundamentele geometriese faktor van die plaat wat oorheers is deur die meetkunde van die plaat self, is wel funksioneel bewys, asook dat dit optree volgens Hall effek teorie. Verder is daar gevind dat die wins wat selfs lae voorwaartse wins bipolêre transistors bydra tot die sein, meer as die verlies wat die meetkundige faktor veroorsaak op die Hall effek kan herwin. Dié meetmetode dra ook minder ruis by met vergelyking tot tipiese tradisionele meetmetodes soos operasionele versterkers, wat vir Hall spanning versterking gebruik word. Die voorgestelde meetmetode skep dus ‘n baie eenvoudige meettegniek wat versoenbaar is met standaard CMOS tegnologie prosesse. / Thesis (PhD)--University of Pretoria, 2014. / lk2014 / Electrical, Electronic and Computer Engineering / PhD / unrestricted