• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 21
  • 2
  • 2
  • 1
  • Tagged with
  • 25
  • 25
  • 25
  • 25
  • 25
  • 5
  • 4
  • 4
  • 4
  • 3
  • 3
  • 3
  • 3
  • 3
  • 3
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Circuit-reduction techniques and application to high-speed systems and interconnects /

Gunupudi, Pavan, January 1900 (has links)
Thesis (Ph.D.) - Carleton University, 2002. / Includes bibliographical references (p. 136-146). Also available in electronic format on the Internet.
2

Motion control of a wafer stage a design approach for speeding up IC production /

Roover, Dick de. January 1900 (has links)
Thesis (doctoral)--Technische Universiteit Delft, 1997. / Vita. Includes bibliographical references (p. 267-282) and index.
3

Motion control of a wafer stage a design approach for speeding up IC production /

Roover, Dick de. January 1900 (has links)
Thesis (doctoral)--Technische Universiteit Delft, 1997. / Vita. Includes bibliographical references (p. 267-282) and index.
4

Data flow description with VHLD

Lo, I-Lung. January 1990 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 1990. / Thesis Advisor(s): Lee, Chin-Hwa Second Reader: Cotton, Mitchell L. "December 1990." Description based on title screen as viewed on April 1, 2010. DTIC Identifier(s): Computer Aided Design, High Level Languages, Computerized Simulation, Theses, VHSIC (Very High Speed Integrated Circuits), VHDL (VHSIC Hardware Description Language). Author(s) subject terms: W-4 Computer, PC, TAR, RAM, ACC, ALU, B_REG, IR, Controller, Test_Bench, VHDL. Includes bibliographical references (p. 113). Also available in print.
5

Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations.

Xie, Dong Hui, Carleton University. Dissertation. Engineering, Electrical. January 1992 (has links)
Thesis (M. Eng.)--Carleton University, 1992. / Also available in electronic format on the Internet.
6

An ultra-compact antenna test system and its analysis in the context of wireless clock distribution

Bomstad, Wayne Roger. January 2002 (has links)
Thesis (M.S.)--University of Florida, 2002. / Title from title page of source document. Includes vita. Includes bibliographical references.
7

A wireless clock distribution system using an external antenna

Li, Ran. January 2005 (has links)
Thesis (Ph. D.)--University of Florida, 2005. / Title from title page of source document. Document formatted into pages; contains 143 pages. Includes vita. Includes bibliographical references.
8

CMOS intra-chip wireless clock distribution

Guo, Xiaoling. January 2005 (has links)
Thesis (Ph. D.)--University of Florida, 2005. / Title from title page of source document. Document formatted into pages; contains 139 pages. Includes vita. Includes bibliographical references.
9

HIGH FREQUENCY DIELECTRIC PROPERTIES OF POLYIMIDES FOR MULTILAYER INTERCONNECT STRUCTURES

Hinedi, Mohamad Fahd, 1964- January 1987 (has links)
One of the most important electrical requirements in high performance electronic systems or high speed integrated circuits, is to process larger numbers of electrical signals at much higher speeds. Signal propagation delay must be minimized in order to maximize signal velocities. Therefore, material with low dielectric constant and low dissipation factor is being sought. In this thesis research measurements of dielectric constant and dissipation factor were performed on commercially available polyimides that are used in multilayer interconnect structures. Capacitor structures with a polyimide dielectric were measured up to a 1GHz frequency and 220°C temperature. Polyimides were concluded to be compatible for use in high performance systems such as multilayer interconnect structures.
10

A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE

Wang, Xiao-Lin, 1955- January 1986 (has links)
No description available.

Page generated in 0.1466 seconds