published_or_final_version / Electrical Engineering / Master / Master of Philosophy

The Discrete Cosine Transform is used in many image and video compression standards. Many methods have been developed for efficiently computing the Discrete Cosine Transform including flowgraph algorithms, distributed arithmetic and two-dimensional decompositions. A new architecture based on distributed arithmetic is presented for computing the Discrete Cosine Transform and it's inverse. The main objective of the design is to minimize the area of the VLSI implementation while maintaining the throughput necessary for video and image compression standards such as MPEG and JPEG. Several improvements have been made compared to previously published distributed arithmetic architectures. These include elimination of four lookup tables and implementation of the lookup tables using logic instead of ROM. A model of the proposed architecture was written in C. The model was used to verify the accuracy of the architecture and to do JPEG compression on a series of test images. Behavioral simulations were performed with a hardware model written in the Verilog hardware description language. These behavioral simulations verify that the hardware implementation matches the C model. The model was synthesized using the Synopsis synthesis tool. The gate count and clock rate of the design were estimated using the synthesis results. / Graduation date: 1997