La course à la miniaturisation requiert l'introduction d'architectures de transistors innovantes enremplacement des technologies conventionnelles sur substrat de silicium. Ainsi la technologie UTBB-FDSOI permet d'améliorer notablement l'intégrité électrostatique et assure une transition progressive vers les structures 3D multigrilles. Ces dispositifs diffèrent des structures conventionnelles par la présence d'un oxyde enterré qui va non seulement modifier l'électrostatique mais également introduire une nouvelle interface de type Si/SiO2 sujette à d'éventuelles dégradations. Par ailleurs, la réduction des dimensions des transistors s'accompagne d'une augmentation de la dispersion des paramètres électriques. En parallèle, le vieillissement de ces transistors introduit une forme additionnelle de variabilité : la variabilité temporelle, qu'il convient d'intégrer à cette composante moyenne de dégradation. Ce travail de thèse est développé sur quatre chapitres, où nous nous intéressons dans le premier chapitre aux évolutions technologiques nécessaires pour passer des technologies CMOS standards (40LP, 28LP) à cette technologie UTBB-FDSOI. Puis dans le second chapitre, nous abordons la dégradation moyenne des transistors et l'impact de l'architecture sur la fiabilité des dispositifs, étudiés sur les mécanismes de dégradations NBTI et HCI. Le troisième chapitre donne au niveau transistor une description analytique et physique de la variabilité temporelle induite par le NBTI. Enfin, cette variabilité temporelle est intégrée au niveau cellules SRAM dans le quatrième chapitre afin de prédire les distributions des tensions minimums de fonctionnement (Vmin) des mémoires SRAM. / The classical CMOS structure is reaching its scaling limits at the 20nm node and innovative architectures of transistors are required to replace these conventional Bulk transistors. UTBB-FDSOI transistors can improve significantly the electrostatic integrity and ensure a smooth transition to 3D multi-gates devices that will be required for sub-10nm nodes. The main difference compared to conventional transistor is related to the integration of a buried oxide (BOX) underneath the silicon film. This latter impacts the electrostatic behavior of these devices and introduces an additional Si/SiO2 interface which may be degraded due to ageing. It is then necessary to evaluate its impact on the NBTI and HCI reliability mechanisms. Besides, transistor scaling leads to an increasing variability which translates into an increased dispersion of the electrical parameters of the transistors. Meanwhile, time dependent variability due to ageing needs to be added to the average degradation component. This PhD done in STMicroelectronics R&D center is divided into four chapters: in the first one, the main technological developments necessary to keep on sustaining Moore's law requirements resulting in the UTBBFDSOI structure introduction is discussed. Then in the second chapter the architecture impact on the average reliability mechanism is discussed at transistor and Ring Oscillators' levels. In the third chapter, the time dependent variability due to NBTI is described and compared to time-zero variability. Finally the last chapter focuses on the SRAM cells reliability and a method is developed to predict minimum operating voltage (Vmin) distributions of SRAM memory.

Indiana University-Purdue University Indianapolis (IUPUI) / In this dissertation, a beyond-CMOS approach to Static Random Access Memory (SRAM) design is investigated using exploratory transistors including Tunnel Field Effect Transistor (TFET), Carbon Nanotube Field Effect Transistor (CNFET) and Graphene NanoRibbon Field Effect Transistor (GNRFET). A Figure-of-Merit (FOM) based comparison of 6-transistor (6T) and a modified 8-transistor (8T) single-port SRAMs designed using exploratory devices, and contemporary devices such as a FinFET and a CMOS process, highlighted the performance benefits of GNRFETs and power benefits of TFETs. The results obtained from the this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array of 256-bitcells. CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 uW, while TFET-based SRAM bitcell show the best overall average and static power consumption at 4.79 uW and 57.8 pW respectively. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write and hold static noise margins at 201 mV, 438 mV and 413 mV respectively. Further, the modification of 8T-SRAMs via dual wordlines for individually controlling read and write operations for uni-directional transistors TFET and CNFET show improvement in read static noise margin (RSNM). In dual wordline CNFET 8T-SRAM, an RSNM improvement of approximately 23.6x from 6 mV to 142 mV was observed by suppressing the read wordline (RWL) from a nominal supply of 0.71 V down to 0.61 V. In dual wordline TFET 8T-SRAM, an RSNM improvement of approximately 16.2x from 5 mV to 81 mV was observed by suppressing the RWL from a nominal supply of 0.6 V down to 0.3 V. Next, the dissertation explores whether the robustness of SRAM arrays can be improved. Specifically, the robustness related to noise margin during the write operation was investigated by implementing a negative bitline (NBL) voltage scheme. NBL improves the write static noise margin (WSNM) of the SRAM bitcells in the row of the array to which the data is written during a write operation. However, this may cause degraded hold static noise margin (HSNM) of un-accessed cells in the array. Applying a negative wordline voltage (NWL) on un-accessed cells during NBL shows that the NWL can counter the degraded HSNM of un-accessed cells due to NBL. The scheme, titled as NBLWL, also allows the supply of a lower NBL, resulting in higher WSNM and write-ability benefits of accessed row. By applying a complementary negative wordline voltage to counter the half-select condition in columns, the WSNM of cells in accessed rows was boosted by 10.9% when compared to a work where no negative bitline was applied. In addition, the HSNM of un-accessed cells remain the same as in the case where no negative bitline was implemented. Essentially, a 10.9% boost in WSNM without any degradation of HSNM in un-accessed cells is observed. The dissertation also focuses on the impact of process-related variations in SRAM arrays to correlate and characterize silicon data to simulation data. This can help designers remove pessimistic margins that are placed on critical signals to account for expected process variation. Removing these pessimistic margins on critical data paths that dictate the memory access time results in performance benefits for the SRAM array. This is achieved via an in-situ silicon monitor titled SRAM process and ageing sensor (SPAS), which can be used for silicon and ageing characterization, and silicon debug. The SPAS scheme is based on a process variation tolerant technique called RAZOR that compares the data arriving on the output of the sense amplifiers during the read operation. This scheme can estimate the impact of process variation and ageing induced slow-down on critical path during read operation of an array with high accuracy. The estimation accuracy in a commercially available 65nm CMOS technology for a 16x16 array at TT, and global SS and FF corners at nominal supply and testing temperature were found to be 99.2%, 94.9% and 96.5% respectively. Finally, redundant columns, an architectural-level scheme for tolerating failing SRAM bitcells in arrays without compromising performance and yield, is studied. Redundant columns are extra columns that are programmed when bitcells in the regular columns of an array are slower or have higher leakage than expected post-silicon. The regular columns are often permanently disabled and remain unused for the chip lifetime once redundant columns are enabled. In the SRRC scheme proposed in this thesis, the regular columns are only temporarily disabled, and re-used at a later time in chip life cycle once the previously awakened redundant columns become slower than the disabled regular columns. Essentially, the scheme can identify and temporarily disable the slowest column in an array until other mitigating factors slow down active columns. This allows the array to operate at a memory access time closer to the target access time regardless of other mitigating factors slowing down bitcells in arrays during chip life cycle. An approximate 76.4% reduction in memory access time was observed from a 16x16 array from simulations in a commercially available 65nm CMOS technology with respect to a work where no redundancy was employed.