The Westinghouse Induction Time Klement Overload Relay, Type CO, a relay operating on the same principle as an alternating current watt-hour meter, is considerably affected in its time of operation when non-sinusoidal waves of potential are applied. If the potential wave applied has a flat top or depressed peak or if the wave has a lagging peak, that is, its maximum instantaneous value occurs more than 90 degrees after the beginning of the cycle, the operation of the relay is accelerated. If the wave of potential applied to the relay reaches its peak more than 90 degrees and less than 180 degrees after the beginning of the cycle, the operation of the relay is retarded from what it would be with a sinusoidal potential applied. The operation of a General Electric Time Current Overload Relay, Type PAC, a plunger type relay with an air bellows time delay, is, in general, retarded in operation by the application of non-sinusoidal potential waves. The operation may be slightly accelerated, however, if the wave distortion is slight, the current setting is low, and the distortion is such that the peak of the wave is flat or lagging. The effect of the wave distortion on other relays requires more study. / Master of Science

A modern system-on-chip (SoC) integrates a range of analog, digital, and mixed-signal building blocks, each with a dedicated voltage domain to maximize energy efficiency. On-chip low-drop-out regulators (LDOs) are widely used to implement these voltage domains due to their advantages of high power density and the ease of integration to a complementary metal-oxide-semiconductor (CMOS) process. Recently, digital LDOs have gained large attention for their low input voltage support for emerging sub-mW SoCs, portability across designs, and process scalability. However, some of the major drawbacks of a conventional digital LDO design are (i) the trade-off between control loop latency and power dissipation which demands a large output capacitor, (ii) failure to address the performance degradations caused by the parasitics in a practical power grid, and (iii) insufficient power-supply-rejection-ratio (PSRR) and large ripple in the output voltage. Chapters 2 through 4 of this thesis present my research on the design and circuit techniques for improving the aforementioned challenges in fully-integrated digital LDOs. The first work implements a hybrid event- and time-driven control in the digital LDO architecture to improve the response and settling time-related metrics over the existing designs. The second work presents a power delivery system consisting of 9 distributed event-driven digital LDOs for supporting a spatially large digital load. The proposed distributed LDO design achieves large improvements in the steady-state and non-steady-state performances compared to a single LDO design. In the third work, we prototype a digital LDO based on new current-source power-FETs to achieve a high PSRR and low output voltage ripple. Lastly, on-chip voltage regulators have recently found usefulness in hardware security applications. An on-chip LDO can be used to improve the side-channel attack (SCA) resistance of a cryptographic core with design modifications to the classical LDO architecture. However, the existing designs incur non-negligible overheads in performance, power, and silicon area due to the conventional active-for-all-encryption-rounds architecture. In the last chapter, we propose a detection-driven activation technique to achieve a near-zero energy-delay-product (EDP) overhead in a SCA resilient digital LDO. In this architecture, the LDO can detect an attack attempt and enable SCA protection only if an attack is detected.

The formulation of an accurate data base consisting of system state variable values is an initial and critical step in the economical and secure operation of modern power systems. The Least Median of Squares (LMS) estimator is ideal in the sense that it can provide a good state estimate despite high percentages of bad data and multiple bad leverage points. The estimator is, however, computationally intensive. In this thesis, an efficient algorithm is developed and implemented to increase the overall speed of the LMS estimator. The algorithm generates measurement samples in a manner that allows use of the resampling technique i.e., they make the system observable and also ensure that each measurement has a nearly equal probability of appearing in each of the measurement samples. / Master of Science

The work presented in this text concentrates on three aspects of voltage stability studies: analysis and determination of suitable proximity indicators, design of an effective real-time monitoring system, and determination of appropriate emergency control techniques. A simulation model of voltage collapse was built as analytical tool on 39-bus, 10-generator power system model. Voltage collapse was modeled as a saddle-node bifurcation of the system dynamic model reached by increasing the system loading. Suitable indicators for real-time monitoring were found to be the minimum singular value of power flow Jacobian matrix and generated reactive powers. A study of possibilities for reducing the number of measurements of voltage phasors needed for voltage stability monitoring was also made. The idea of load bus coherency with respect to voltage dynamics was introduced. An algorithm was presented which determines the coherent clusters of load buses in a power system based on an arbitrary criterion function, and the analysis completed with two proposed coherency criteria. Very good agreement was obtained by simulation between the results based on accurate and approximate measurements of the state vector. An algorithm was presented for identification of critical sets of loads in a voltage unstable power system, defined as a subset of loads whose changes have the most pronounced effect on the changes of minimum singular value of load flow Jacobian or generated reactive powers. Effects of load shedding of critical loads were investigated by simulation and favorable results obtained. An investigation was also done by sensitivity analysis of proximity indicators of the effects that locations and amounts of static var compensation have on the stability margin of the system. Static compensation was found to be of limited help when voltage instabilities due to heavy system loading occur in power systems. The feasibility of implementation of the analyses and algorithms presented in this text relies on development of a feasible integrated monitoring and control hardware. The phasor measurement system which was designed at Virginia Polytechnic institute and State University represents an excellent candidate for implementation of real-time monitoring and control procedures. / Ph. D.