Scheduling is one of the most important issues in the planning of manufacturing systems. This research focuses on solving the test scheduling problem which arises in semiconductor manufacturing environment. Semiconductor wafer devices undergo a series of test processes conducted on computer-controlled test stations at various temperatures. A test process consists of both setup operations and processing operations on the test stations. The test operations occur in a specified order on the wafer devices, resulting in precedence constraints for the schedule. Furthermore, the assignment of the wafer devices to test stations and the sequence in which they are processed affects the time required to finish the test operations, resulting in sequence dependent setup times. The goal of this research is to develop a realistic model of the semiconductor wafer test scheduling problem and provide heuristics for scheduling the precedence constrained test operations with sequence dependent setup times. A mathematical model is presented and two heuristics are developed to solve the scheduling problem with the objective of minimizing the makespan required to test all wafer devices on a set of test stations. The heuristic approaches generate a sorted list of wafer devices as a dispatching sequence and then schedule the wafer lots on test stations in order of appearance on the list. An experimental analysis and two case studies are presented to validate the proposed solution approaches. In the two case studies, the heuristics are applied to actual data from a semiconductor manufacturing facility. The results of the heuristic approaches are compared to the actual schedule executed in the manufacturing facility. For both the case studies, the proposed solution approaches decreased the makespan by 23-45% compared to the makespan of actual schedule executed in the manufacturing facility. The solution approach developed in this research can be integrated with the planning software of a semiconductor manufacturing facility to improve productivity. / Master of Science

La thèse intitulée "Conception, caractérisation et optimisation d’un transistor à effet de champ haute tension en Carbure de Silicium (SiC) et de leur diode associée", s’est déroulée au sein du laboratoire AMPERE sous la direction du Prof. D. PLANSON. Des premiers démonstrateurs de JFET ont été réalisés. Le blocage du JFET n'est pas efficace, ceci étant lié aux difficultés de réalisation technologique. Le premier travail a consisté en leur caractérisation précise puis en leur simulation, en tenant compte des erreurs de processus de fabrication. Ensuite, un nouveau masque a été dessiné en tenant en compte des problèmes technologiques identifiés. Les performances électriques de la nouvelle génération du composant ont ainsi démontré une amélioration importante au niveau de la tenue en tension. Dans le même temps, de nouveaux problèmes se sont révélés, qu’il sera nécessaire de résoudre dans le cadre de travaux futurs. Par ailleurs, les aspects de tenue en court-circuit des JFETs en SiC commercialement disponibles ont été étudiés finement. Les simulations électrothermiques par TCAD ont révélé les modes de défaillances. Ceci a permis d'établir finalement des modèles physiques valables pour les JFETs en SiC. / Silicon carbide (SiC) has higher critical electric field for breakdown and lower intrinsic carrier concentration than silicon, which are very attractive for high power and high temperature power electric applications. In this thesis, a new 3.3kV/20A SiC-4H JFET is designed and fabricated for motor drive (330kW). This breakdown voltage is beyond the state of art of the commercial unipolar SiC devices. The first characterization shows that the breakdown voltage is lower (2.5kV) than its theoretical value. Also the on-state resistance is more important than expected. By means of finite element simulation the origins of the failure are identified and then verified by optical analysis. Hence, a new layout is designed followed by a new generation of SiC-4H JFET is fabricated. Test results show the 3.3kV JFET is developed successfully. Meanwhile, the electro-thermal mechanism in the SiC JFETs under short circuit is studied by means of TCAD simulation. The commercial 1200V SIT (USCi) and LV-JFET (Infineon) are used as sample. A hotspot inside the structures is observed. And the impact the bulk thickness and the canal doping on the short circuit capability of the devices are shown. The physical models validated by this study will be used on our 3.3kV once it is packaged.