Threshold Logic technology is conceived as the crucial alternate emerging technology to CMOS implementation in nanoelectronic era and the realization of complex functionalities is becoming an increasingly promising approach in the deep sub-micron design era. The gate that is implemented with threshold logic is called a Threshold Logic Gate (TLG). The logic output value of a Threshold Logic Gate (TLG) depends on the weighted sum of its inputs. Manufactured weights in the threshold logic gates (TLGs) may differ from the designed values and significantly affects the fault coverage. A novel fault model for weight defects is proposed. Also an Automatic Test Pattern Generation (ATPG) tool has been implemented that uses the fault model to detect whether the circuit is malfunctioning due to such weight-related defects. A novel design methodology is presented in this work to design complex TLG networks that are tolerant to manufacturing shortcomings. It uses a procedure to identify the optimum fault tolerant design of any given k-input TLG. Extensive research has been done in the development of synthesis methodologies in the past, predominantly greedy. A fault tolerance aware synthesis methodology is proposed.